Analog to digital converter stage

Patent metadata

Field	Value
Publication number	US-11082056-B2
Application number	US-201916692371-A
Country	US
Kind code	B2
Filing date	Nov 22, 2019
Priority date	Mar 8, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

First claim

What is claimed is:

1. A capacitive digital to analog converter (DAC) arrangement for utilization within a data converter, comprising:
a first DAC slice to receive a signal via an input line of the first DAC slice, the first DAC slice having a first resist ance coupled in series on the input line of the first DAC slice; and
a second DAC slice coupled in parallel with the first DAC slice, the second DAC slice to receive the signal via an input line of the second DAC slice, the second DAC slice having a second resistance coupled in series on the input line of the second DAC slice;
wherein sampling performance of the first DAC slice matches sampling performance of the second DAC slice.

2. The capacitive DAC arrangement of claim 1 , wherein;
a first analog representation output by the first DAC slice is formed as a function of a first sampled input voltage sampled by the first DAC slice and a first digital word applied to the first DAC slice; and
a second analog representation output by the second DAC slice is formed as a function of a second sampled input voltage sampled by the second DAC slice and a second digital word applied to the second DAC slice.

3. The capacitive DAC arrangement of claim 1 , wherein;
the first DAC slice has a first time constant;
the second DAC slice has a second time constant; and
the second time constant is within a threshold value of the first time constant.

4. The capacitive DAC arrangement of claim 1 , wherein:
the first DAC slice includes a first capacitor and a first transistor;
the second DAC slice includes a second capacitor and a second transistor; and
a ratio of an area of the first capacitor and an area of the second capacitor is the same as a ratio of a width to length ratio of the first transistor and a width to length ratio of the second transistor.

5. The capacitive DAC arrangement of claim 1 , wherein:
the first DAC slice and the second DAC slice are to be coupled to an analog-to-digital converter (ADC) stage;
a data manipulation block is to be coupled between the ADC stage and the first DAC slice, and between the ADC stage and the second DAC slice; and
the data manipulation block is to individually set digital words for the first DAC slice and the second DAC slice.

6. The capacitive DAC arrangement of claim 1 , wherein:
the first DAC slice includes:
a first set of capacitors to perform sampling;
a second set of capacitors to perform sampling; and
a first coupling capacitor coupled between the first set of capacitors and the second set of capacitors; and

the second DAC slice includes:
a third set of capacitors to perform sampling;
a fourth set of capacitors to perform sampling; and
a second coupling capacitor coupled between the third set of capacitors and the fourth set of capacitors.

7. The capacitive DAC arrangement of claim 1 , wherein:
a reference line for the first DAC slice includes a first switch and a first buffer coupled in parallel with a second switch between the first DAC slice and a reference input of the first DAC slice;
the first switch is to couple the first DAC slice to the first buffer and the second switch is to couple the first DAC slice directly to the reference input of the first DAC slice;
a reference line for the second DAC slice includes a third switch and a second buffer coupled in parallel with a fourth switch between the second DAC slice and a reference input of the second DAC slice; and
the third switch is to couple the second DAC slice to the second buffer and the fourth switch is to couple the second DAC slice directly to the reference input of the second DAC slice.

8. The capacitive DAC arrangement of claim 1 , wherein the data converter is an analog to digital converter.

9. An analog to digital converter (ADC), comprising:
an ADC stage to receive an input signal and produce a digital representation of the input signal; and
a residue digital to analog converter (DAC), comprising:
a first DAC slice coupled to the ADC stage, the first DAC slice to sample the input signal via a first line and the first DAC slice having a first resistance coupled in series with a first switch on the first line; and
a second DAC slice coupled to the ADC stage in parallel with the first DAC slice, the second DAC slice to sample the input signal via a second line and the first DAC slice having a second resistance coupled in series with a second switch on the second line;
wherein the first DAC slice and the second DAC slice are to form a residue representing a difference between the input signal and a voltage produced by the residue DAC when driven with the digital representation of the input signal from the ADC stage.

10. The ADC of claim 9 , further comprising:
a buffer amplifier selectively connectable to the residue DAC to provide an internal reference signal generated by the buffer amplifier to the residue DAC during a first phase of operation of the ADC stage.

11. The ADC of claim 10 , further comprising:
switching circuitry to provide an external reference signal generated by an external reference source to the residue DAC in place of the internal reference signal during a second phase of operation of the ADC stage.

12. The ADC of claim 9 , wherein the ADC receives bit trials from a further ADC and uses the bit trials from the further ADC as a starting point for bit trials of the ADC.

13. The ADC of claim 9 , wherein the first DAC slice, the first switch, the second DAC slice, and the second switch are controllable to operate in an interleaved manner.

14. The ADC of claim 9 , wherein the first DAC slice, the first switch, the second DAC slice, and the second switch are controllable to operate in a parallel manner.

15. The ADC of claim 9 , wherein sampling performance of the first DAC slice matches the sampling performance of the second DAC slice.

16. A digital to analog converter (DAC) slice for utilization in a data converter, comprising:
a capacitor coupled to an output of the DAC slice;
a set of transistors coupled to the capacitor, the set of transistors to operate as a switch to couple the capacitor to different lines of the DAC slice; and
a resistance coupled in series with a transistor of the set of transistors on an input line of the DAC slice;
wherein a size of the capacitor from a second capacitor in a second DAC slice by a first ratio, and a width to length ratio of the set of transistors differs from a further set of transistors in the further DAC slice by the first ratio.

17. The DAC slice of claim 16 , wherein:
the capacitor and the set of transistors define a time constant of the DAC slice;
the DAC slice is to be coupled in parallel with the second DAC slice in the data converter; and
the time constant of the DAC slice is to be substantially matched with a time constant of the second DAC slice.

18. The DAC slice of claim 16 , wherein width to length ratios of transistors within the set of transistors are substantially equal.

19. The DAC slice of claim 16 , wherein:
the DAC slice is to be coupled to an analog-to-digital converter (ADC) stage of the data converter; and
the DAC slice is to be utilized in production of a residue related to the ADC stage.

20. The DAC slice of claim 16 , wherein:
the DAC slice is to be coupled in parallel with further DAC slices in the data converter; and
sampling performance of the DAC slice matches sampling performance of the further DAC slices.

21. A digital to analog converter (DAC) slice for utilization in a data converter,

Assignees

• Analog Devices International Unlimited Co

Inventors

• Bodnar Rares
• Ahmad Asif
• Hurrell Christopher Peter

Classifications

• H03M1/42

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/0845

  of power supply variations, e.g. ripple · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/802

  using capacitors, e.g. neuron-mos transistors, charge coupled devices · CPC title