Method of linearizing the transfer characteristic by dynamic element matching

Patent metadata

Field	Value
Publication number	US-10511316-B2
Application number	US-201816053455-A
Country	US
Kind code	B2
Filing date	Aug 2, 2018
Priority date	Mar 8, 2018
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

First claim

What is claimed is:

1. A residue-forming sampling digital to analog converter, the residue-forming sampling digital to analog converter being responsive to a digital word which comprises a first part and a second part, wherein the residue-forming sampling digital to analog converter comprises:
a plurality of cooperating digital to analog converters arranged in parallel, wherein:
the plurality of cooperating digital to analog converters receive respective data words from a data word generator,
the data words comprise a shared portion and an additional portion;
the shared portion represents the first part of the digital word following shuffling by the data word generator, and
the additional portion encodes values belonging to the second part of the digital word.

2. The residue-forming sampling digital to analog converter of claim 1 , wherein:
the data word generator comprises at least two shufflers, and
the at least two shufflers comprise:
a first shuffler arranged to receive the first part of the digital word and to generate shared shuffled data signals to a first group of conversion elements of the cooperating digital to analog converters, and
a second shuffler arranged to receive at least part of the second part of the digital word and to generate shuffled data signals relating to bits not belonging to the first part of the digital word,
wherein the shuffled data signals are used to control the first group of conversion elements.

3. The residue-forming sampling digital to analog converter of claim 1 , wherein:
the data word generator comprises cascaded shufflers, and
the cascaded shufflers comprise:
a first shuffler to receive a plurality of bits for controlling a first group of conversion elements, and
a second shuffler to receive bits for controlling some of a second group of conversion elements, and to receive information from the first part of the digital word.

4. The residue-forming sampling digital to analog converter of claim 3 , in which the second shuffler also receives data signals from the first shuffler.

5. The residue-forming sampling digital to analog converter of claim 4 , in which the second shuffler supplies an input to the first shuffler.

6. The residue-forming sampling digital to analog converter of claim 5 , wherein:
at least one conversion element of the first group of conversion elements in each cooperating digital to analog converter, which is controlled based on a bit value associated with the second group of conversion elements, is shuffled into different conversion elements in the plurality of the cooperating digital to analog converters for each operation of the cooperating digital to analog converters.

7. The residue-forming sampling digital to analog converter of claim 1 , wherein:
an input to the data word generator further includes at least one additional bit signal for injecting a known signal into the plurality of cooperating digital to analog converters for use in one or more of: a dithering of an output, and a calibration procedure.

8. The residue-forming sampling digital to analog converter of claim 1 , wherein:
the plurality of cooperating digital to analog converters comprise a plurality of slices,
each slice comprises a plurality of conversion elements,
the conversion elements are sub-divided into a first group of conversion elements and a second group of conversion elements,
the first and second groups of conversion elements are connected together by an intermediate component, and
at least one conversion element of the first group of conversion elements in each slice is controlled in response to a bit value based on data words whose weight is appropriate for the second group of conversion elements in at least some of the plurality of slices.

9. The residue-forming sampling digital to analog converter of claim 8 , wherein:
the first group of conversion elements is operable to digitize a word to a least significant bit resolution of the first group of conversion elements, and
at least one conversion element of the first group of conversion elements is controlled in response to a bit value based on the data words of the second group of conversion elements and has a size equal to a least significant bit.

10. The residue-forming sampling digital to analog converter of claim 2 , wherein:
bit values representing a binary encoded value for the first group of conversion elements are converted by the data word generator to thermometer or unary encoded form and shuffled into element control signals for a plurality of conversion elements of the first group of conversion elements, and
the conversion elements of the first group of conversion elements are selected on a shuffled or randomized basis within each slice.

11. The residue-forming sampling digital to analog converter of claim 2 , wherein:
with an exception of at least one element of the first group of conversion elements, each cooperating digital to analog converter receives the same shuffled data word for the conversion elements therein.

12. The residue-forming sampling digital to analog converter of in claim 1 , wherein:
the cooperating digital to analog converters are formed of switched capacitors.

13. The residue-forming sampling digital to analog converter of claim 1 , wherein the residue-forming sampling digital to analog converter is a residue-forming stage of an analog to digital converter.

14. The residue-forming sampling digital to analog converter of claim 1 , wherein:
each cooperating digital to analog converter includes a main digital to analog converter part, and
at least some of the cooperating digital to analog converters include a sub-digital to analog converter part, wherein the main digital to analog converter part converts the first part of the digital word, the first part representing a more significant part of the digital word, and the sub-digital to analog converter converts bits of lesser significance of the digital word.

15. The residue-forming sampling digital to analog converter of claim 1 , wherein:
the plurality of cooperating digital to analog converters comprise K converters selected from a bank of L converters,
K and L are integers,
L is greater than K, and
a selection of the K converters is dynamically chosen.

16. The residue-forming sampling digital to analog converter of claim 1 , wherein:
a position of the additional portion is shuffled within the cooperating digital to analog converters.

17. A digital to analog converter comprising:
a plurality of DAC slices, wherein:
each slice is segmented into a main DAC part and a sub-DAC part,
the main DAC part to output an analog value relating to a plurality of most significant bits of a digital word, and
the sub-DAC part to output a value associated with a plurality of bits of lesser significance, wherein some of bit values associated with the sub-DAC part are shuffled across the main DAC part of the DAC slices.

18. The digital to analog converter of claim 17 , wherein the digital to analog converter is a sampling capacitor charge-sharing digital to analog converter.

19. The digital to analog converter of claim 17 , in which the main DAC parts of each slice are nominally identical in terms of capacitance or nominally identical in terms of sampling time constant when in a sampling mode.

20. A digital to analog converter for converting a digital word to an analog value, wherein:
the digital word comprises a first part and a second part, and
the digital to analog converter comprises a plural

Assignees

• Analog Devices Global Unlimited Co

Inventors

• Bodnar Rares
• Maurino Roberto S
• Hurrell Christopher Peter
• Ahmad Asif

Classifications

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/1033

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/067 Primary

  using different permutation circuits for different parts of the digital signal · CPC title