Analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9331709-B2
Application number	US-201414162572-A
Country	US
Kind code	B2
Filing date	Jan 23, 2014
Priority date	Apr 20, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

First claim

What is claimed is:

1. An analog-to-digital converter system comprising:
a capacitive digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value; and
a control circuit comprising a scrambler circuit for selectively permutating bit values of digital codes applied to the capacitive digital-to-analog converter; the control circuit configured to sequentially apply a plurality of digital codes to the capacitive digital-to-analog converter during an analog-to-digital conversion operation to derive an encoded numerical representation of the combination of the analog signal value and the analog dither value.

2. The analog-to-digital converter system of claim 1 , wherein the scrambler circuit is configured for dynamic element matching.

3. The analog-to-digital converter system of claim 1 , wherein the scrambler circuit is configured to operate as a scrambler for a mismatch-shaping encoder.

4. The analog-to-digital converter system of claim 1 , wherein the scrambler circuit is configured to suppress in a signal band an error induced by mismatch of weighting factors of a plurality of input terminals of the capacitive digital-to-analog converter.

5. The analog-to-digital converter system of claim 1 , wherein the scrambler circuit is configured to substantially randomize an error signal induced by mismatch of weighting factors of a first plurality of input terminals of the capacitive digital-to-analog converter.

6. The analog-to-digital converter system of claim 5 , further comprising a dither generator circuit configured to provide the analog dither value; the dither generator circuit configured to substantially randomize an error signal induced by mismatch of weighting factors of a second plurality of input terminals of the capacitive digital-to-analog converter.

7. The analog-to-digital converter system of claim 1 , wherein a calculation of an encoded numerical representation of the analog signal value includes calculating a weighted sum of a plurality of substantially stochastic bit-value-differences.

8. The analog-to-digital converter system of claim 7 , wherein a substantially stochastic bit-value-difference in the plurality of substantially stochastic bit-value-differences is characterized by a relatively lower spectral power density in a signal band.

9. The analog-to-digital converter system of claim 1 , further comprising a dither generator circuit configured to apply a digital dither code to the capacitive digital-to-analog converter at a sampling instance.

10. The analog-to-digital converter system of claim 9 , wherein the control circuit is configured to combine the digital dither code with a digital code derived to represent the combination of the analog signal value and the analog dither value to derive an encoded numerical representation of the analog signal value.

11. The analog-to-digital converter system of claim 9 , wherein a bit value of the digital dither code is a substantially random quantity.

12. The analog-to-digital converter system of claim 9 , wherein the dither generator circuit is configured to substantially randomize and induce stochastic properties for a plurality of bit values in a digital code derived by the control circuit to represent the combination of the analog signal value and the analog dither value.

13. The analog-to-digital converter system of claim 9 , wherein the dither generator circuit is configured to be responsive to a digital code derived by the control circuit in a preceding analog-to-digital conversion operation to represent a sampled value.

14. The analog-to-digital converter system of claim 9 , wherein the dither generator circuit in a first mode of operation is configured to set a bit value of the digital dither code responsive to a bit value of a digital code derived by the control circuit in a preceding analog-to-digital conversion operation to represent a sampled value.

15. The analog-to-digital converter system of claim 14 , wherein the dither generator circuit is configured to switch between the first mode of operation and a second mode of operation, the dither generator circuit in the second mode of operation configured to set said bit value of said digital dither code on a substantially random basis.

16. The analog-to-digital converter system of claim 1 , including circuitry configured to store digital codes for weighting factors of the capacitive digital-to-analog converter estimated after the analog-to-digital converter system is manufactured.

17. The analog-to-digital converter system of claim 1 , including circuitry configured to perform at least one step of successive approximation during the analog-to-digital conversion operation.

18. The analog-to-digital converter system of claim 1 , wherein the control circuit is configured to provide an indication of a residue of the combination of the analog signal value and the analog dither value with respect to a digital code applied to the capacitive digital-to-analog converter.

19. The analog-to-digital converter system of claim 1 , wherein the scrambler circuit is configured to apply at least two distinct permutations during the analog-to-digital conversion operation.

20. The analog-to-digital converter system of claim 1 , wherein the control circuit is configured to derive a first digital code representing the combination of the analog signal value and the analog dither value when the scrambler circuit is configured to apply a first permutation; the control circuit is further configured to derive a second digital code representing the combination of the analog signal value and the analog dither value when the scrambler circuit is configured to apply a second permutation distinct from the first permutation; the control circuit is further configured to combine the first digital code, the second digital code, and a digital dither code to derive an encoded numerical representation of the analog signal value.

21. The analog-to-digital converter system of claim 1 , further comprising a digital filter configured to limit a noise bandwidth.

22. The analog-to-digital converter system of claim 1 , including circuitry configured to apply an averaging operation.

23. The analog-to-digital converter system of claim 1 , wherein the control circuit is configured to substantially randomize and suppress in a signal band a spectral power density of a quantization error.

24. The analog-to-digital converter system of claim 1 , further comprising a switched-capacitor filter configured to receive a residue signal comprising a quantization error.

25. The analog-to-digital converter system of claim 24 , wherein the switched-capacitor filter is configured to randomize and suppress the quantization error in a signal band.

Assignees

• Linear Techn Inc

Inventors

• Steensgaard-Madsen Jesper

Classifications

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/0668 Primary

  the selection being based on the output of noise shaping circuits for each element · CPC title

• H03M1/201 Primary

  by dithering · CPC title

• H03M1/0641

  the dither being a random signal · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title