Memory device with bit lines disconnected from NAND strings for fast programming

Patent metadata

Field	Value
Publication number	US-11081180-B2
Application number	US-202016842112-A
Country	US
Kind code	B2
Filing date	Apr 7, 2020
Priority date	Jun 5, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

First claim

We claim:

1. An apparatus, comprising:
a first block of memory cells, the first block comprising a first stack of alternating conductive and dielectric layers formed on a substrate, the conductive layers are connected to the memory cells, the memory cells are arranged in a first set of NAND strings extending vertically upward from the substrate to a top of the first stack, and the first set of NAND strings comprises rows of data-storing NAND strings interleaved with rows of dummy NAND strings;
an insulation layer at the top of the first stack;
a first set of bit lines interleaved with a second set of bit lines above the insulation layer; and
a respective conductive via in the insulation layer for each NAND string of the rows of data-storing NAND strings, a bottom of each respective conductive via contacts a top of each respective NAND string of the rows of data-storing NAND strings, a top of each respective conductive via contacts a respective bit line of the first set of bit lines to electrically connect the first set of bit lines to the data-storing NAND strings, and a bottom of the insulation layer contacts a top of each respective dummy NAND string to electrically disconnect the second set of bit lines from the dummy NAND strings.

2. The apparatus of claim 1 , wherein:
each respective conductive via extends vertically upward in the insulation layer from the top of each respective NAND string of the rows of data-storing NAND strings to a bottom of the respective bit line of the first set of bit lines.

3. The apparatus of claim 1 , wherein:
a respective conductive via is not provided in the insulation layer for each NAND string of the rows of dummy NAND strings.

4. The apparatus of claim 1 , wherein:
each bit line of the first set of bit lines extends horizontally directly over a respective row of the data-storing NAND strings in the first block; and
each bit line of the second set of bit lines extends horizontally directly over a respective row of the dummy NAND strings in the first block.

5. The apparatus of claim 1 , wherein:
each of the data-storing NAND strings and the dummy NAND strings comprises a respective vertical pillar extending from the substrate to the top of the first stack.

6. The apparatus of claim 1 , further comprising:
a bit line driver connected to the first set of bit lines and the second set of bit lines, the bit line driver is configured to drive the first set of bit lines while floating voltages of the second set of bit lines during programming of the data-storing NAND strings.

7. The apparatus of claim 1 , further comprising:
a second block of memory cells, the second block comprising a second stack of alternating conductive and dielectric layers formed on the substrate, the conductive layers of the second block are connected to the memory cells of the second block, the memory cells of the second block are arranged in a second set of NAND strings extending vertically upward from the substrate to a top of the second stack, and the second set of NAND strings comprises a first set of rows of data-storing NAND strings interleaved with a second set of rows of data-storing NAND strings, wherein:
each respective data-storing NAND string in the first set of rows of data-storing NAND strings is electrically connected to a respective bit line of the first set of bit lines; and
each respective data-storing NAND string in the second set of rows of data-storing NAND strings is electrically connected to a respective bit line of the second set of bit lines.

8. The apparatus of claim 7 , further comprising:
a bit line driver connected to the first set of bit lines and the second set of bit lines, the bit line driver is configured to drive the first set of bit lines while floating voltages of the second set of bit lines during programming of the data-storing NAND strings in the first block, and to drive the first set of bit lines and the second set of bit lines during programming of the first set of rows of data-storing NAND strings and the second set of rows of data-storing NAND strings of the second block.

9. The apparatus of claim 7 , further comprising:
a bit line driver connected to the first set of bit lines and the second set of bit lines, the bit line driver is configured to allocate a first time period when changing a voltage of the first set of bit lines during programming of the data-storing NAND strings in the first block, and to allocate a second time period, greater than the first time period, when changing a voltage of the first set of bit lines and the second set of bit lines during programming of the first set of rows of data-storing NAND strings and the second set of rows of data-storing NAND strings of the second block.

10. The apparatus of claim 7 , further comprising:
an insulation layer at the top of the second stack; and
conductive vias extending through the insulation layer at the top of the second stack, the conductive vias electrically connect each respective data-storing NAND string in the first set of rows of data-storing NAND strings to the respective bit line of the first set of bit lines and each respective data-storing NAND string in the second set of rows of data-storing NAND strings to the respective bit line of the second set of bit lines.

11. The apparatus of claim 7 , further comprising:
a bit line driver connected to the first set of bit lines and the second set of bit lines, wherein a distance between the bit line driver and the second block is greater than a distance between the bit line driver and the first block.

Assignees

• Sandisk Technologies Llc

Inventors

• Yang Xiang
• Tseng Huai-Yuan
• Dutta Deepanshu

Classifications

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title