Fast read for non-volatile storage

Patent metadata

Field	Value
Publication number	US-9703719-B2
Application number	US-201514927838-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	May 8, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.

First claim

What is claimed is:

1. A circuit, comprising:
a plurality of sense amplifiers and a plurality of caches, one cache per sense amplifier, wherein each sense amplifier is connected to a respective memory cell in a word line via a respective bit line, the respective bit lines comprise a first set of every other bit line and a second set of every other bit line, and the plurality of sense amplifiers and the plurality of caches are arranged in a plurality of tiers including a first tier and a second tier, wherein:
the first tier comprises N sense amplifiers including N/2 sense amplifiers associated with the first set of every other bit line, N/2 sense amplifiers associated with the second set of every other bit line, and N caches including a first set of N/2 caches and a second set of N/2 caches; and
the second tier comprises N sense amplifiers including N/2 sense amplifiers associated with the first set of every other bit line, N/2 sense amplifiers associated with the second set of every other bit line, and N caches including a first set of N/2 caches and a second set of N/2 caches; and
the circuit further comprising a data bus of size N bits comprising input N/2 paths which are connected to the first set of N/2 caches of the first tier and to the first set of N/2 caches of the second tier in a first mode, and which are connected to the second set of N/2 caches of the first tier and to the second set of N/2 caches of the second tier in a second mode.

2. The circuit of claim 1 , further comprising:
in the first tier, a first selection line connected to the N caches of the first tier; and
in the second tier, a second selection line connected to the N caches of the second tier.

3. The circuit of claim 2 , further comprising:
a control circuit, the control circuit is configured to cause the first selection line to select the N caches of the first tier in the first mode and the second mode, and to cause the second selection line to select the N caches of the second tier in the first mode and the second mode.

4. The circuit of claim 2 , further comprising:
a first set of N/2 cache access lines connected to the first set of N/2 caches of the first tier, one cache access line per cache;
a second set of N/2 cache access lines connected to the second set of N/2 caches of the first tier, one cache access line per cache;
a third set of N/2 cache access lines connected to the first set of N/2 caches of the second tier, one cache access line per cache;
a fourth set of N/2 cache access lines connected to the second set of N/2 caches of the second tier, one cache access line per cache;
a first set of N/2 transistors, each transistor of the first set of N/2 transistors is connected to one of the N/2 cache access lines of the first set of N/2 cache access lines, to one of the N/2 cache access lines of the second set of N/2 cache access lines and to the data bus; and
a second set of N/2 transistors, each transistor of the second set of N/2 transistors is connected to one of the N/2 cache access lines of the third set of N/2 cache access lines, to one of the N/2 cache access lines of the fourth set of N/2 cache access lines and to the data bus.

5. The circuit of claim 1 , further comprising:
in the first tier, one selection line connected to the first set of N/2 caches of the first tier and another selection line connected to the second set of N/2 caches of the first tier; and
in the second tier, one selection line connected to the first set of N/2 caches of the second tier and another selection line connected to the second set of N/2 caches of the second tier.

6. The circuit of claim 5 , further comprising:
a control circuit, the control circuit, in the first mode, is configured to cause the one selection line of the first tier to select the first set of N/2 caches of the first tier and to cause the one selection line of the second tier to select the first set of N/2 caches of the second tier and, in the second mode, is configured to cause the another selection line of the first tier to select the second set of N/2 caches of the first tier and to cause the another selection line of the second tier to select the second set of N/2 caches of the second tier.

7. The circuit of claim 5 , further comprising:
a first set of N cache access lines connected to the N caches of the first tier, one cache access line per cache, wherein each input path of a first set of N/2 input paths of the data bus is connected to a respective cache in the first set of N/2 caches of the first tier in the first mode and to a respective cache in the second set of N/2 caches of the first tier in the second mode; and
a second set of N cache access lines connected to the N caches of the second tier, one cache access line per cache, wherein each input path of a second set of N/2 input paths of the data bus is connected to a respective cache in the first set of N/2 caches of the second tier in the first mode and to a respective cache in the second set of N/2 caches of the second tier in the second mode.

8. The circuit of claim 1 , wherein:
the data bus has a first part of size N/2 bits and a second part of size of N/2 bits;
in the first mode, concurrently the first part is connected to the first set of N/2 caches of the first tier and the second part is connected to the first set of N/2 caches of the second tier; and
in the second mode, concurrently the first part is connected to the second set of N/2 caches of the first tier and the second part is connected to the second set of N/2 caches of the second tier.

9. The circuit of claim 1 , wherein:
the first set of every other bit line comprises even-numbered bit lines and the second set of every other bit line comprises odd-numbered bit lines, or the first set of every other bit line comprises odd-numbered bit lines and the second set of every other bit line comprises even-numbered bit lines.

10. The circuit of claim 1 , further comprising a control circuit, the control circuit in a programming operation is configured to:
in the first mode, concurrently transfer a first half of a first word of data from the data bus to the first set of N/2 caches of the first tier and transfer a first half of a second word of data from the data bus to the first set of N/2 caches of the second tier; and
in the second mode, concurrently transfer a second half of the first word of data from the data bus to the second set of N/2 caches of the first tier and transfer a second half of the second word of data from the data bus to the second set of N/2 caches of the second tier.

11. The circuit of claim 10 , wherein the control circuit in the programming operation is configured to:
transfer the first half of the first word of data from the first set of N/2 caches of the first tier to a first half of the sense amplifiers of the first tier and transfer the second half of the first word of data from the second set of N/2 caches of the first tier to a second half of the sense amplifiers of the first tier; and
transfer the first half of the second word of data from the first set of N/2 caches of the second tier to a first half of the sense amplifiers of the second tier and transfer the second half of the second word of data from the second set of N/2 caches of the second tier to a second half of the sense amplifiers of the second tier.

12. The circuit of claim 1 , further comprising a control circuit, the control circuit in a read operation is configured to:
in the first mode at a first time, transfer a first half of a first word of data from the first set of N/2 caches of the first tier to the data bus and transfer a first half of a second word of data from the first set of N/2 caches

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Balakrishnan Gopinath
• Siau Chang
• Kato Yosuke
• Tsai Wanfang
• Zaitsu Shingo

Classifications

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title