Adaptive selective bit line pre-charge for current savings and fast programming

Patent metadata

Field	Value
Publication number	US-9595345-B2
Application number	US-201414454702-A
Country	US
Kind code	B2
Filing date	Aug 7, 2014
Priority date	Aug 7, 2014
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory cell;
a sense circuit connected to the memory cell via a bit line;
a control circuit, the control circuit configured to perform a program operation for the memory cell to program the memory cell to a target data state and selectively test the memory cell using the sense circuit during the program operation, the selective testing includes charging the bit line; and
a processor connected to the sense circuit, the processor configured to make a determination that the target data state matches one data state of a set of predetermined data states and, in response to the determination, cause the sense circuit to perform the selective testing of the memory cell relative to each data state of the set of predetermined data states, and cause the sense circuit to not charge the bit line during selective testing of another memory cell relative to a data state which is not in the set of predetermined data states.

2. The apparatus of claim 1 , wherein:
the control circuit, to selectively test the memory cell, is configured to apply a set of verification signals to the memory cell; and
the set of verification signals comprises a different level for each data state of the set of predetermined data states.

3. The apparatus of claim 2 , wherein:
the set of verification signals comprises at least one additional level used for testing memory cells relative to at least one additional data state; and
the memory cell is not tested relative to the at least one additional data state.

4. The apparatus of claim 2 , wherein:
the sense circuit, to perform the selective testing of the memory cell, is configured to make a determination of whether the memory cell is in a conductive state during each of the different levels of the set of verification signals.

5. The apparatus of claim 1 , wherein:
the processor is configured to activate the sense circuit during the selective testing of the memory cell relative to each data state of the set of predetermined data states and to not activate the sense circuit during testing of an additional memory cell relative to an additional data state.

6. The apparatus of claim 5 , wherein:
the memory cells are connected to a common word line.

7. The apparatus of claim 1 , wherein:
the processor is configured to discard sensing results from the selective testing of the memory cell relative to one or more data states in the set of predetermined data states which are a mismatch to the target data state of the memory cell, and to transfer to a managing circuit, sensing results from the selective testing of the memory cell relative to a data state in the set of predetermined data states which matches the target data state of the memory cell.

8. The apparatus of claim 1 , wherein:
the sense circuit is configured to make a determination of whether the memory cell is in a conductive state during the selective testing of the memory cell relative to each data state of the set of predetermined data states.

9. The apparatus of claim 1 , wherein:
the set of predetermined data states comprises different data states during different programming phases of the program operation.

10. The apparatus of claim 1 , wherein:
the set of predetermined data states comprises a different number of data states during different programming phases of the program operation.

11. The apparatus of claim 1 , further comprising:
latches associated with the sense circuit, wherein the processor is configured to read the latches to determine the target data state.

12. A method, comprising:
programming a memory cell to a target data state during a program operation, the programming comprises applying a set of verification signals to the memory cell, wherein a number of verification signals in the set of verification signals is less than a number of target data states in a plurality of available target data states, determining that the target data state of the memory cell is tested by one of the verification signals, and in response to the determining that the target data state of the memory cell is tested by the one of the verification signals, sensing the memory cell while applying each of the verification signals;
discarding sensing results from sensing of the memory cell during one or more of the verification signals which are a mismatch to the target data state of the memory cell; and
transferring to a managing circuit, sensing results from sensing of the memory cell during one of the verification signals which is a match to the target data state of the memory cell.

13. The method of claim 12 , wherein:
the set of verification signals is a function of a current phase among multiple phases of the program operation.

14. The method of claim 12 , wherein:
the sensing the memory cell while applying each of the verification signals comprises activating a sense circuit for the memory cell while applying each of the verification signals.

15. The method of claim 14 , wherein:
the activating the sense circuit comprises charging a bit line connected to the sense circuit.

16. The method of claim 12 , wherein:
the programming the memory cell comprises performing a plurality of program-verify iterations, wherein each program-verify iteration comprises a program portion and a verify portion, and the set of verification signals is applied to the memory cell and the sensing of the memory cell is performed during the verify portion of at least one of the program-verify iterations.

17. An apparatus, comprising:
a memory cell;
a sense circuit connected to the memory cell; and
a control circuit, the control circuit configured to:
perform a program operation for the memory cell to program the memory cell to a target data state, wherein to perform the program operation, the control circuit is configured to apply a set of verification signals to the memory cell, the set of verification signals comprises a first portion for testing relative to a first set of data states and a second portion for testing relative to a second set of data states;
make a first determination that the target data state of the memory cell is among the first set of data states;
in response to the first determination, activate the sense circuit during the first portion of the set of verification signals to sense the memory cell relative to each data state of the first set of data states;
make a second determination that the target data state of the memory cell is not among the second set of data states; and
in response to the second determination, not activate the sense circuit during the second portion of the set of verification signals.

18. The apparatus of claim 17 , wherein the control circuit is configured to:
during the first portion of the set of verification signals, activate sense circuits of memory cells for which a target data state is among the first set of data states, and not activate sense circuits of memory cells for which a target data state is among the second set of data states; and
during the second portion of the set of verification signals, activate sense circuits of memory cells for which a target data state is among the second set of data states, and not activate sense circuits of memory cells for which a target data state is among the first set of data states.

19. The apparatus of claim 17 , wherein:
the first portion of the set of verification signals comprises a different level for each data state of the first set of data states; and
the sense circuit is configured to determine whet

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Mui Man L
• Koh Yee Lih
• Li Yenlung
• Hsu Cynthia

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title