Semiconductor memory device using grounded dummy bit lines

Patent metadata

Field	Value
Publication number	US-9653167-B2
Application number	US-201514687177-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Feb 19, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
in the case that three directions intersecting each other are assumed to be a first direction, a second direction, and a third direction,
a memory cell array including a plurality of memory cells and a first wiring line layer and second wiring line layer disposed sequentially above the memory cells in the third direction, the first wiring line layer including a first wiring line and a first dummy wiring line that are aligned in the first direction and have the second direction as a longer direction, and the second wiring line layer including a second wiring line and a second dummy wiring line that are aligned in the first direction and have the second direction as a longer direction; and
a control circuit that controls an access operation on the memory cells,
the first wiring line layer including a plurality of the first wiring lines and a plurality of the first dummy wiring lines aligned alternately one at a time in the first direction,
the second wiring line layer including a plurality of the second wiring lines and a plurality of the second dummy wiring lines aligned alternately one at a time in the first direction, and
during the access operation by the control circuit, the first wiring line being electrically connected to one of the memory cells, the second wiring line being electrically connected to another of the memory cells, and the first dummy wiring line and the second dummy wiring line being fixed at a certain first potential.

2. The semiconductor memory device according to claim 1 , wherein the first potential is a ground potential.

3. The semiconductor memory device according to claim 1 , wherein
the memory cell array includes a first via contacting the second wiring line and extending in the third direction from the second wiring line to a side of the memory cells, and
the first dummy wiring line is divided in a disposition region of the first via.

4. The semiconductor memory device according to claim 3 , wherein the first via is a columnar body having the third direction as a longer direction, and the first via contacts the second wiring line at a side surface.

5. The semiconductor memory device according to claim 1 , wherein the memory cell array includes an intermediate electrode at an intermediate position of the memory cells and the first wiring line layer in the third direction, the intermediate electrode being set to the first potential.

6. The semiconductor memory device according to claim 5 , wherein the memory cell array includes a second via, the second via contacting the first dummy wiring line and the intermediate electrode.

7. A semiconductor memory device, comprising:
in the case that three directions intersecting each other are assumed to be a first direction, a second direction, and a third direction,
a memory cell array including a plurality of memory cells connected in series and a word line layer, first bit line layer, and second bit line layer disposed sequentially above the memory cells in the third direction, the word line layer including a plurality of word lines that function as control gates of the memory cells, the first bit line layer including a first bit line and a first dummy bit line that are aligned in the first direction and have the second direction as a longer direction, and the second bit line layer including a second bit line and a second dummy bit line that are aligned in the first direction and have the second direction as a longer direction; and
a control circuit that controls an access operation on the memory cells,
the first bit line layer including a plurality of the first bit lines and a plurality of the first dummy bit lines aligned alternately one at a time in the first direction,
the second bit line layer including a plurality of the second bit lines and a plurality of the second dummy bit lines aligned alternately one at a time in the first direction, and
during the access operation by the control circuit, the first bit line being electrically connected to one of the memory cells, the second bit line being electrically connected to another of the memory cells, and the first dummy bit line and the second dummy bit line being fixed at a certain first potential.

8. The semiconductor memory device according to claim 7 , wherein the first potential is a ground potential.

9. The semiconductor memory device according to claim 7 , wherein
the memory cell array includes a first via contacting the second bit line and extending in the third direction from the second bit line to a side of the memory cells, and
the first dummy bit line is divided in a disposition region of the first via.

10. The semiconductor memory device according to claim 9 , wherein the first via is a columnar body having the third direction as a longer direction, and the first via contacts the second bit line at a side surface.

11. The semiconductor memory device according to claim 7 , wherein the memory cell array includes an intermediate electrode at an intermediate position of the word line layer and the first bit line layer in the third direction, the intermediate electrode being set to the first potential.

12. The semiconductor memory device according to claim 11 , wherein the memory cell array includes a second via, the second via contacting the first dummy bit line and the intermediate electrode.

13. The semiconductor memory device according to claim 7 , wherein
the second bit line is disposed at the same position in the first direction as the first dummy bit line, and the second dummy bit line is disposed at the same position in the first direction as the first bit line.

14. A semiconductor memory device comprising:
in the case that three directions intersecting each other are assumed to be a first direction, a second direction, and a third direction,
a memory cell array including a plurality of memory cells and a first wiring line layer and second wiring line layer disposed sequentially above the memory cells in the third direction, the first wiring line layer including a first wiring line and a first dummy wiring line that are aligned in the first direction and have the second direction as a longer direction, and the second wiring line layer including a second wiring line and a second dummy wiring line that are aligned in the first direction and have the second direction as a longer direction; and
a control circuit that controls an access operation on the memory cells,
the second wiring line being disposed at the same position in the first direction as the first dummy wiring line,
the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and
during the access operation by the control circuit, the first wiring line being electrically connected to one of the memory cells, the second wiring line being electrically connected to another of the memory cells, and the first dummy wiring line and the second dummy wiring line being fixed at a certain first potential.

15. The semiconductor memory device according to claim 14 , wherein the first potential is a ground potential.

16. The semiconductor memory device according to claim 14 , wherein
the first wiring line layer includes a plurality of the first wiring lines and a plurality of the first dummy wiring lines aligned alternately one at a time in the first direction, and
the second wiring line layer includes a plurality of the second wiring lines and a plurality of the second dummy wiring lines aligned alternately one at a time in the first direction.

17. Th

Assignees

• Toshiba Kk

Inventors

• Takekida Hideto

Classifications

• H01L27/11524

  Electricity · mapped topic

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title