Method and apparatus for performing synthesis for field programmable gate array embedded feature placement

Patent metadata

Field	Value
Publication number	US-11080019-B2
Application number	US-201816022857-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jan 12, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A method for designing and configuring a system on a field programmable gate array (FPGA) is disclosed. A portion of the system that is implemented greater than a predetermined number of times is identified. A structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion is generated. The identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time. Synthesizing, placing, and routing the other portions of the system on the FPGA is performed in accordance with the structural netlist. The FPGA is configured with a configuration file that includes a design for the system that reflects the synthesizing, placing, and routing, wherein the configuring physically transforms resources on the FPGA to implement the system.

First claim

What is claimed is:

1. A method for designing and configuring a system on a field programmable gate array (FPGA), comprising:
identifying a portion of the system that is implemented greater than a predetermined number of times;
generating a structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion, wherein the identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time;
synthesizing, placing, and routing the other portions of the system on the FPGA in accordance with the structural netlist; and
configuring the FPGA with a configuration file that includes a design for the system that reflects the synthesizing, placing, and routing, wherein the configuring physically transforms resources on the FPGA to implement the system.

2. The method of claim 1 , wherein generating the structural netlist comprises constructing a leaf that includes a densely packed structural netlist of the portion that utilizes more than a predetermined percentage of resources occupying an area of the leaf.

3. The method of claim 2 further comprising identifying a plurality of different functionally equivalent design variations for implementing the leaf on the FPGA.

4. The method of claim 3 , wherein the plurality of different design variations for implementing the leaf includes a first variation that utilizes only logic array blocks, a second variation that utilizes a first combination of logic array blocks and digital signal processing blocks, and a third variation that utilizes a second combination of logic array blocks and digital signal processing blocks.

5. The method of claim 3 further comprising generating a layout of a plurality of leaves on the FPGA.

6. The method of claim 5 , wherein generating the layout accounts for a flow of data into and out of the system.

7. The method of claim 5 , wherein generating the layout comprises determining which of the plurality of different functionally equivalent design variations for implementing the leaf on the FPGA are to be used for the layout of the plurality leaves.

8. The method of claim 5 , wherein generating the layout comprises utilizing each of the plurality of different functionally equivalent design variations for implementing the leaf on the FPGA for the layout of the plurality leaves.

9. The method of claim 5 further comprising modifying the layout to account for discontinuities on the FPGA.

10. The method of claim 5 further comprising modifying the layout to reduce congestion.

11. The method of claim 10 , wherein the congestion is measured using a number of inputs and outputs, a total area of the one of the leaves, a hamming weight, and a Manhattan distance of one of the plurality of leaves.

12. The method of claim 9 further comprising replicating the modified layout for the design of the system.

13. The method of claim 1 further comprising:
identifying a second portion of the system that is implemented greater than the predetermined number of times;
generating another structural netlist that describes how to implement the second portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the second portion, wherein the identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time.

14. The method of claim 1 , wherein the portion comprises a processor.

15. The method of claim 1 , wherein the portion comprises a memory.

16. The method of claim 1 , wherein the portion comprises a logic function.

17. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing and configuring a system on a field programmable gate array (FPGA), comprising:
identifying a first portion of the system that is implemented greater than a predetermined number of times;
generating a structural netlist that describes how to implement the first portion a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion;
identifying a second portion of the system that is implemented greater than the predetermined number of times; and
generating another structural netlist that describes how to implement the second portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the second portion, wherein the identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time.

18. The non-transitory computer readable medium of claim 17 , wherein the method further comprises:
synthesizing, placing, and routing the system on the FPGA in accordance with the structural netlist and the another structural netlist; and
configuring the FPGA with a configuration file that includes a design for the system that reflects the synthesizing, placing, and routing, wherein the configuring physically transforms resources on the FPGA to implement the system.

19. A system designer for designing and configuring a system on a field programmable gate array (FPGA), comprising:
a synthesis for embedded feature placement (SEFP) unit that identifies a portion of the system that is implemented greater than a predetermined number of times, and that generates a structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA by leveraging a repetitive nature of implementing the portion, wherein the identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time;
a synthesis unit that synthesizes other portions of the system on the FPGA with the portion of the system in accordance with the structural netlist;
a placement unit that places the other portions of the system with the portion of the system on the FPGA in accordance with the structural netlist; and
an assembly unit that configures the FPGA with a configuration file that includes a design for the system that reflects the synthesizing and placing, wherein the configuring physically transforms resources on the FPGA to implement the system.

20. The system designer of claim 19 , wherein the SEFP unit comprises a leaf function construction unit that constructs a leaf that includes a densely packed structural netlist of the portion that utilizes more than a predetermined percentage of resources occupying an area of the leaf.

21. The system designer of claim 20 , wherein the leaf function construction unit further identifies a plurality of different functionally equivalent design variations for implementing the leaf on the FPGA.

22. The system designer of claim 21 , wherein the plurality of different design variations for implementing the leaf includes a first variation that utilizes only logic array blocks, a second variation that utilizes a first combination of logic array blocks and digital signal processing blocks, and a third variation that utilizes a second combination of logic array blocks and digital signal processing blocks.

23. The system designer of claim 22 further comprising a high-level layout unit that

Assignees

• Intel Corp

Inventors

• Langhammer Martin
• Baeckler Gregg William
• Gribok Sergey

Classifications

• G06F7/5306 Primary

  with row wise addition of partial products (G06F7/5324 takes precedence) · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F7/5312 Primary

  using carry save adders · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title