Methods for incremental circuit physical synthesis

Patent metadata

Field	Value
Publication number	US-10936772-B1
Application number	US-201615233855-A
Country	US
Kind code	B1
Filing date	Aug 10, 2016
Priority date	Aug 10, 2016
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform multiple rounds of incremental physical synthesis, incremental timing analysis, and incremental legalization operations. Each round may involve performing multiple different physical synthesis transforms on the design that are individually rejected until transforms that satisfy legality constraints and improve timing for the logic design are found and incorporated into the netlist. The configuration data may then be generated using the netlist. In this way, the logic design may be incrementally altered and verified during the physical synthesis process. This prevents the need for rejecting or accepting an entire batch logic changes to the netlist even when only some of the changes are non-ideal, thus optimizing circuit performance as well as the compile time required to implement the logic design on the integrated circuit.

First claim

What is claimed is:

1. A method of using logic design equipment to generate configuration data for loading onto a target device, wherein the target device implements a logic design when loaded with the configuration data, the method comprising:
placing a set of basic logic elements (BLEs) at locations in the logic design;
performing a first set of incremental physical synthesis transforms on the set of BLEs;
performing a first set of timing analysis operations based on the first set of incremental physical synthesis transforms;
after performing the first set of incremental physical synthesis transforms and after performing the first set of timing analysis operations, packing the BLEs into logic array blocks (LABs) in the logic design;
performing a second set of incremental physical synthesis transforms on the LABs in the logic design, wherein performing the second set of incremental physical synthesis transforms comprises identifying respective subsets of physical synthesis transforms; and
performing a second set of timing analysis operations, wherein performing the second set of timing analysis operations comprises performing a corresponding timing analysis operation for each of the respective subsets of physical synthesis transforms.

2. The method defined in claim 1 , wherein performing the second set of incremental physical synthesis transforms comprises performing an operation selected from the group consisting of re-packing the LABs in the logic design and deleting at least one of the LABs in the logic design.

3. The method defined in claim 1 , wherein the basic logic elements comprise a logic element selected from the group consisting of:
a look-up table, a flip-flop, a block random access memory element, a digital signal processor, and a carry chain.

4. The method defined in claim 1 , wherein performing the first set of incremental physical synthesis transforms and performing the second set of incremental physical synthesis transforms comprise altering a netlist.

5. The method defined in claim 4 , further comprising:
assembling the configuration data based on the altered netlist file; and
transmitting the configuration data to a configuration device that configures the target device using the configuration data assembled by the assembler.

6. The method defined in claim 1 , wherein the first set of incremental physical synthesis transforms comprises a physical synthesis transform selected from the group consisting of:
a retiming operation, a slack equalization operation, a LAB packing operation, a LAB unpacking operation, a placement adjustment operation, a look-up table input rotation operation, a logic duplication operation, and a critical path re-synthesis (CPR) operation.

7. The method defined in claim 1 , further comprising:
after performing the second set of incremental physical synthesis transforms and after performing the second set of timing analysis operations, moving the LABs to modified locations within the logic design.

8. The method defined in claim 7 , further comprising:
after moving the LABs to the modified locations, performing a third set of incremental physical synthesis transforms and a third set of timing analysis operations on the logic design.

9. The method defined in claim 8 , further comprising:
identifying legality constraints associated with the target device;
performing,
based on the identified legality constraints, a first legalization operation on the logic design after packing the BLEs into the LABs in the logic design and before moving the LABs to the modified locations within the logic design; and
performing, based on the identified legality constraints, a second legalization operation on the logic design after moving the LABs to the modified locations and before performing the third set of incremental physical synthesis transforms and the third set of timing analysis operations.

10. The method defined in claim 9 , wherein performing the second legalization operation comprises:
determining whether any logic blocks in the logic design are located at a first of the modified locations prior to moving the LABs to the modified locations;
in response to determining that no logic blocks are located at the first modified location, placing a first of the LABs at the first modified location; and
in response to determining that a given logic block is located at the first modified location, moving the given logic block out of the first modified location and placing the first packed LAB at the first modified location after moving the given logic block out of the first modified location.

11. The method defined in claim 8 , further comprising:
after performing the third set of incremental physical synthesis transforms and the third set of timing analysis operations, performing placement refinement operations on the LABs in the logic design;
after performing the placement refinement operations, performing a fourth set of incremental physical synthesis transforms and a fourth set of timing analysis operations on the logic design;
saving a netlist file that identifies the logic design after performing the fourth set of incremental physical synthesis transforms and the fourth set of timing analysis operations;
assembling the configuration data based on the saved netlist file; and
transmitting the configuration data to a configuration device that configures the target device using the configuration data assembled by the assembler.

12. A method of operating a system to implement a logic design on a programmable integrated circuit using configuration data, the method comprising:
with logic design equipment in the system, packing basic logic elements (BLEs) in the logic design within logic array blocks (LABs) in the logic design;
with the logic design equipment, performing a first set of incremental physical synthesis transforms on the packed BLEs based on a first set of timing analysis operations, wherein performing the first set of incremental physical synthesis transforms comprises:
updating the logic design from a prior state to an updated state by incorporating a first physical synthesis transform;
selectively reverting the logic design from the updated state to the prior state based on a corresponding timing analysis operation associated with the first physical synthesis transform; and
performing additional physical synthesis transforms and corresponding timing analysis operations after updating and selectively reverting the logic design;

with the logic design equipment, placing the LABs at selected locations within the logic design that satisfy legality constraints associated with the programmable integrated circuit; and
with the logic design equipment, after placing the LABs at the selected locations, performing a second set of incremental physical synthesis transforms on the logic design based on a second set of timing analysis operations.

13. The method defined in claim 12 , wherein packing the BLEs within the LABs comprises packing the BLEs within adaptive logic modules (ALMs) in the LABs, the method further comprising:
with the logic design equipment, refining placement of the BLEs, ALMs, and LABs in the logic design after performing the second set of incremental physical synthesis transforms; and
with the logic design equipment, performing a third set of incremental physical synthesis transforms on the logic design based on a third set of timing analysis operations after refining the placement of the BLEs, ALMs, and LABs in the logic design.

14. The method defined in claim 12 , further comprising:
with the logic design equipment in the system, generating a netl

Assignees

• Altera Corp

Inventors

• Iyer Mahesh A
• Walker Robert
• Kamath Vasudeva M

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/3312

  Timing analysis · CPC title