System design flow with runtime customizable circuits

Patent metadata

Field	Value
Publication number	US-10691856-B1
Application number	US-201815943519-A
Country	US
Kind code	B1
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A computer-implemented design flow can include, within a circuit design for an integrated circuit, determining a portion of the circuit design that is a candidate for implementation as a runtime customizable circuit and determining implementation options for the runtime customizable circuit. The design flow can also include generating, using computer hardware, a description of the circuit design using the runtime customizable circuit to implement the portion of the circuit design and generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within the integrated circuit. The program code is usable by the embedded processor to parameterize the runtime customizable circuit to create a specific instance of the runtime customizable circuit.

First claim

What is claimed is:

1. A method, comprising:
within a circuit design for an integrated circuit, detecting, using computer hardware, a circuit structure of the circuit design that is a candidate for implementation as a runtime customizable circuit;
determining, using the computer hardware, implementation options for the runtime customizable circuit;
generating, using the computer hardware, a hardware description of the circuit design by replacing the circuit structure within the circuit design with the runtime customizable circuit; and
generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within programmable circuitry of the integrated circuit created by loading a configuration bitstream in the integrated circuit, wherein the program code is usable by the embedded processor to parameterize the implementation of the runtime customizable circuit to implement a particular version of the circuit structure; and
wherein the implementation of the runtime customizable circuit is reprogrammable to implement a different version of the circuit structure by loading different parameterization data from the embedded processor.

2. The method of claim 1 , wherein the program code includes a driver that, when executed by the embedded processor, configures the embedded processor to communicate with the implementation of the runtime customizable circuit.

3. The method of claim 1 , wherein the program code, when executed by the embedded processor, causes the embedded processor to generate parameterization data from a specification, wherein the parameterization data parameterizes the implementation of the runtime customizable circuit.

4. The method of claim 1 , wherein the generating the program code comprises:
generating parameterization data for the implementation of the runtime customizable circuit.

5. The method of claim 4 , further comprising:
generating a compiled binary that is executable by the implementation of the runtime customizable circuit.

6. The method of claim 1 , wherein the generating the program code comprises:
generating additional program code executable by the embedded processor to generate further program code executable by the implementation of the runtime customizable circuit.

7. The method of claim 1 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining input signals to the runtime customizable circuit; and
determining output signals from the runtime customizable circuit.

8. The method of claim 1 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining whether to include trace circuitry coupled to the implementation of the runtime customizable circuit.

9. The method of claim 1 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining whether to include switch circuitry coupled to the implementation of the runtime customizable circuit.

10. The method of claim 1 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining whether to include a clock controller coupled to the implementation of the runtime customizable circuit.

11. A system, comprising:
a first processor configured to initiate operations including:
within a circuit design for an integrated circuit, detecting a circuit structure of the circuit design that is a candidate for implementation as a runtime customizable circuit;
determining implementation options for the runtime customizable circuit;
generating a hardware description of the circuit design by replacing the circuit structure with the circuit design with the runtime customizable circuit; and
generating program code for a second processor embedded in the integrated circuit and coupled to an implementation of the runtime customizable circuit within programmable circuitry of the integrated circuit created by loading a configuration bitstream in the integrated circuit, wherein the program code is usable by the second processor to parameterize the implementation of the runtime customizable circuit to implement a particular version of the circuit structure; and
wherein the implementation of the runtime customizable circuit is reprogrammable to implement a different version of the circuit structure by loading different parameterization data from the embedded processor.

12. The system of claim 11 , wherein the program code includes a driver that, when executed by the second processor, configures the second processor to communicate with the implementation of the runtime customizable circuit.

13. The system of claim 11 , wherein the program code, when executed by the second processor, causes the second processor to generate parameterization data from a specification, wherein the parameterization data parameterizes the implementation of the runtime customizable circuit.

14. The system of claim 11 , wherein the generating the program code comprises:
generating parameterization data for the implementation of the runtime customizable circuit.

15. The system of claim 14 , wherein the first processor is configured to initiate operations further including:
generating a compiled binary that is executable by the implementation of the runtime customizable circuit.

16. The system of claim 11 , wherein the generating the program code comprises:
generating additional program code executable by the second processor to generate further program code executable by the implementation of the runtime customizable circuit.

17. The system of claim 11 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining input signals to the runtime customizable circuit; and
determining output signals from the runtime customizable circuit.

18. The system of claim 11 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining whether to include trace circuitry coupled to the implementation of the runtime customizable circuit.

19. The system of claim 11 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining whether to include switch circuitry coupled to the implementation of the runtime customizable circuit.

20. The system of claim 11 , wherein the determining the implementation options for the runtime customizable circuit comprises:
determining whether to include a clock controller coupled to the implementation of the runtime customizable circuit.

Assignees

• Xilinx Inc

Inventors

• Lysaght Patrick
• Schelle Graham F

Classifications

• G06F30/38 Primary

  Circuit design at the mixed level of analogue and digital signals · CPC title

• G06F30/343

  Logical level · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title