Host-based bit string conversion

Patent metadata

Field	Value
Publication number	US-11080017-B2
Application number	US-201916281587-A
Country	US
Kind code	B2
Filing date	Feb 21, 2019
Priority date	Feb 21, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Systems, apparatuses, and methods related to host-based bit string conversion are described. A conversion component may be deployed on a host computing system and configured to perform operations on bit strings to selectively convert the bit string between various numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The conversion component may comprise a processing device that may be coupled to one or more memory resources. The memory resource of the conversion component may be configured to receive a bit string having a first format. The processing device of the conversion component coupled to the memory resource may be configured to format or convert the bit string to a second format.

First claim

What is claimed is:

1. An apparatus, comprising:
a conversion component memory resource resident on a host computing system and configured to receive, from a memory array resident on a memory device coupled to the host computing system, data comprising a bit string having a first format that supports arithmetic operations to a first level of precision; and
a processing device resident on the host computing system and coupled to the conversion component memory resource, wherein the processing device is configured to:
receive the data from the conversion component memory resource and convert the bit string to yield a converted bit string having a second format that supports arithmetic operations to a second level of precision that is different from the first level of precision; and
transfer the converted bit string to acceleration circuitry comprising logic circuitry and a non-volatile memory resource, the acceleration circuitry resident on the memory device coupled to the host computing system, wherein

the acceleration circuitry is configured to perform, as part of performance of a machine learning operation, an arithmetic operation or a logical operation, or both, using the converted bit string in the absence of an intervening command from the host computing device.

2. The apparatus of claim 1 , wherein the first format comprises a floating-point format and the second format comprises a universal number format or wherein the first format comprises an IEEE 754 format and the second format comprises a Type III universal number format or a posit format.

3. The apparatus of claim 1 , wherein one of the first format or the second format includes a mantissa, a base, and an exponent portion, and wherein the other of the first format or the second format includes a mantissa, a sign, a regime, and an exponent portion.

4. The apparatus of claim 1 , wherein the conversion component memory resource is configured to receive a resultant bit string representing a result of the arithmetic operation or the logical operation, or both, the resultant bit string having the second format, and wherein the processing device is configured to convert the resultant bit string to the first format.

5. The apparatus of claim 1 , wherein the processing device is further configured to perform at least a portion of the arithmetic operation or the logical operation, or both, using the bit string having the second format prior to transferring the converted bit string to the acceleration circuitry.

6. A method, comprising:
receiving, by a conversion component memory resource resident on a host computing system, data stored in a memory array of a memory device coupled to the host computing system and comprising a bit string having a first format that supports arithmetic operations to a first level of precision;
performing, by a processing device coupled to the conversion component memory resource, an operation to convert the bit string to yield a converted bit string having a second format that supports arithmetic operations to a second level of precision that is different from the first level of precision;
transferring the converted bit string to acceleration circuitry comprising logic circuitry and a non-volatile memory resource, the acceleration circuitry resident on the memory device coupled to the host computing system;
performing, using the acceleration circuitry and as part of performance of a machine learning operation, an arithmetic operation or a logical operation, or both, using the converted bit string in the absence of an intervening command from the host computing device; and
writing a result of the arithmetic operation or the logical operation, or both to at least one of the memory array or the host computing system.

7. The method of claim 6 , further comprising performing, by the processing device, a subsequent operation to convert a bit string subsequently received by the conversion component memory resource and having the second format to a second bit string having the first format.

8. The method of claim 6 , further comprising performing the arithmetic operation or the logical operation, or both, using the bit string having the second format as an operand for the arithmetic operation or the logical operation, or both.

9. The method of claim 6 , further comprising performing the operation to convert the bit string from the first format to the second format in response to receiving the bit string having the first format in the absence of an intervening host command.

10. The method of claim 6 , wherein converting, by the processing device, the bit string having the first format to the bit string having the second format comprises converting a floating-point format bit string to a universal number format bit string.

11. A system, comprising:
a host computing system comprising a conversion component memory resource and a processing device; and
a non-volatile memory device comprising acceleration circuitry and a memory array, wherein the non-volatile memory device is coupled to the host computing system, and wherein the acceleration circuitry comprises logic circuitry and a memory resource, and wherein:
the conversion component memory resource is configured to receive a bit string having a first format that supports arithmetic operations to a first level of precision from the memory array;
the processing device is configured to:
convert the bit string to yield a converted bit string having a second format that supports arithmetic operations to a second level of precision;
cause the converted bit string to be transferred to the memory resource of the acceleration circuitry; and

the acceleration circuitry is configured to:
store the converted bit string in the memory resource of the acceleration circuitry;
cause, within the acceleration circuitry, performance of an arithmetic operation or a logical operation, or both, using the converted bit string responsive to receipt of the converted bit string in the absence of an intervening command generated by the host computing system.

12. The system of claim 11 , wherein one of the first format or the second format includes a mantissa, a base, and an exponent portion, and wherein the other of the first format or the second format includes a mantissa, a sign, a regime, and an exponent portion.

13. The system of claim 11 , wherein:
the logic circuitry is further configured to transfer a resultant bit string representing a result of an arithmetic operation or a logical operation, or both, to the conversion component memory resource, the resultant bit string having the second format; and
the processing device is further configured to convert the resultant bit string to the first format.

14. The system of claim 13 , wherein the resultant bit string comprises a Type III universal number format or a posit format, and wherein the first format comprises a floating-point format.

15. The system of claim 13 , wherein the processing device is configured to convert the resultant bit string to the first format responsive to receipt of the resultant bit string by the conversion component memory resource in the absence of an intervening command.

16. The system of claim 11 , wherein the host further comprises an application programming interface configured to control an operation performed by the processing device to convert the bit string to the second format.

17. The system of claim 11 , wherein the acceleration circuitry is further configured to write a result of the arithmetic operation or the logical operation, or both to the memory array or the host, or

Assignees

• Micron Technology Inc

Inventors

• Ramesh Vijay S

Classifications

• H03M7/24 Primary

  Conversion to or from floating-point codes · CPC title

• H03M7/005

  using semiconductor devices · CPC title

• H03M7/28 Primary

  Programmable structures, i.e. where the code converter contains apparatus which is operator-changeable to modify the conversion process · CPC title

• H03M7/14

  Conversion to or from non-weighted codes · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title