Memory device having a controller to enable and disable mode control circuitry of the controller

Patent metadata

Field	Value
Publication number	US-9965208-B1
Application number	US-201313774688-A
Country	US
Kind code	B1
Filing date	Feb 22, 2013
Priority date	Feb 23, 2012
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

Configurable operating mode memory devices are disclosed. In at least one embodiment, a memory device is configurable into one or more operating modes. An array of memory cells can be allocated into one or more partitions where each partition is associated only with a particular mode of operation. In at least one other embodiment, a memory device is configured to store user data in a portion of a memory array and to store data corresponding to a logical function associated with a different operating mode of the memory device in a different portion of the memory array.

First claim

What is claimed is:

1. A memory device, comprising:
a NAND memory array comprising a plurality of NAND strings, wherein each NAND string comprises a plurality of one-transistor memory cells coupled in series with each other; and
a memory controller, comprising master control circuitry and a plurality of mode control circuitries, wherein the mode control circuitries of the plurality of mode control circuitries respectively correspond to operating modes of a plurality of operating modes of the memory device, wherein the master control circuitry is configured to enable and disable one or more of the plurality of mode control circuitries;
wherein a first one of the plurality of operating modes is associated with a first portion of the NAND memory array and a second one of the plurality of operating modes is associated with a second portion of the NAND memory array;
wherein the memory device is further configured to concurrently operate the memory device in two or more different operating modes of the plurality of operating modes; and
wherein the memory device is further configured to operate the first one of the plurality of operating modes and the second one of the plurality of operating modes using a common programming operation to program memory cells of the first portion of the NAND memory array and the second portion of the NAND array, respectively.

2. The memory device of claim 1 , wherein the memory device is further configured to only access the first portion of the NAND memory array in response to enabling a first one of the plurality of mode control circuitries to operate the memory device in the first one of the plurality of operating modes and to only access the second portion of the NAND memory array in response to enabling a second one of the plurality of mode control circuitries to operate the memory device in the second one of the plurality of operating modes.

3. The memory device of claim 1 , wherein the first and the second portions of the NAND memory array comprise first and second partitions of the NAND memory array.

4. The memory device of claim 1 , wherein the master control circuitry is configured to reconfigure the memory controller by disabling one or more of the plurality of mode control circuitries that are enabled and/or by enabling one or more of the plurality of mode control circuitries that are disabled.

5. The memory device of claim 4 , wherein the master control circuitry is further configured to reallocate the NAND memory array responsive to reconfiguring the memory controller.

6. The memory device of claim 1 , wherein each portion of the NAND memory array comprises a respective NAND string of the plurality of NAND strings.

7. The memory device of claim 1 , wherein the plurality of operating modes includes a user data storage operating mode.

8. The memory device of claim 1 , wherein the plurality of operating modes includes a programmable logic device (PLD) operating mode.

9. The memory device of claim 1 , wherein to the plurality of operating modes includes a content addressable memory (CAM) operating mode.

10. A memory device, comprising:
a NAND memory array comprising a plurality of NAND strings, wherein each NAND string comprises a plurality of one-transistor memory cells coupled in series with each other; and
a memory controller, comprising master control circuitry and a plurality of mode control circuitries, the mode control circuitries of the plurality of mode control circuitries respectively corresponding to operating modes of a plurality of operating modes of the memory device, wherein the master control circuitry is configured to configure the memory controller in one configuration by enabling one or more mode control circuitries of the plurality of mode control circuitries and configured to reconfigure the memory controller in a different configuration by enabling one or more different mode control circuitries of the plurality of mode control circuitries, each operating mode facilitating a respective function;
wherein a particular portion of the NAND memory array is associated with a particular one of the plurality of operating modes and is accessed only in response to performing a particular function associated with the particular one of the plurality of operating modes;
wherein the particular portion of the NAND memory array comprises a particular NAND string of the plurality of NAND strings;
wherein the memory device is further configured to concurrently operate the memory device in two or more different operating modes of the plurality of operating modes;
wherein an other portion of the NAND memory array is associated with an other one of the plurality of operating modes; and
wherein the memory device is to program the particular portion of the NAND memory array and the other portion of the NAND memory array using a same programming operation.

11. A memory device, comprising:
a NAND memory array comprising a plurality of NAND strings, wherein each NAND string comprises a plurality of one-transistor memory cells coupled in series with each other; and
a memory controller, comprising master control circuitry and a plurality of mode control circuitries, the mode control circuitries of the plurality of mode control circuitries respectively corresponding to operating modes of a plurality of operating modes of the memory device, wherein the master control circuitry is configured to enable and disable one or more of the plurality of mode control circuitries, wherein a respective function is associated with each operating mode;
wherein a first portion of the NAND memory array is associated with a first one of the plurality of mode control circuitries that corresponds to a first one of the plurality of operating modes and a second portion of the NAND memory array is associated with a second one of the plurality of mode control circuitries that corresponds to a second one of the plurality of operating modes;
wherein the first portion of the NAND memory array is only accessed in response to performing the respective function associated with the first one of the plurality of operating modes and the second portion of the NAND memory array is only accessed in response to performing the respective function associated with the second one of the plurality of operating modes;
wherein the memory device is further configured to concurrently operate the memory device in two or more different operating modes of the plurality of operating modes; and
wherein the memory device is further configured to operate the first one of the plurality of operating modes and the second one of the plurality of operating modes using a common programming operation to program memory cells of the first portion of the NAND memory array and the second portion of the NAND array, respectively.

12. The memory device of claim 11 , wherein the memory device is further configured to store logical data in the first portion of the NAND memory array, where the stored logical data corresponds to a particular logical function.

13. The memory device of claim 12 , wherein the memory device is further configured to change the logical data stored in the first portion of the NAND memory array, where the changed logical data corresponds to a different logical function than the particular logical function.

14. The memory device of claim 12 , wherein the memory device is further configured to store user data in the second portion of the NAND memory array.

15. The memory device of claim 14 , wherein the memory device is further configured to transfer from the memory device the user data stored in the second portion of the NAND mem

Assignees

• Micron Technology Inc

Inventors

• Roohparvar Frankie F
• De Santis Luca
• Vali Tommaso
• Eldredge Kenneth J

Classifications

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0634 Primary

  by changing the state or mode of one or more devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/2263

  using neural networks · CPC title