Signed division in memory

Patent metadata

Field	Value
Publication number	US-2017329577-A1
Application number	US-201615152266-A
Country	US
Kind code	A1
Filing date	May 11, 2016
Priority date	May 11, 2016
Publication date	Nov 16, 2017
Grant date	—

Abstract

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

First claim

What is claimed is:

1 . An apparatus comprising:
a first group of memory cells coupled to a sense line and to a number of first access lines; a second group of memory cells coupled to the sense line and to a number of second access lines; and a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

2 . The apparatus of claim 1 , wherein the controller configured to operate the sensing circuitry to perform the number of operations comprises the controller configured to operate sensing circuitry to perform at least one of a number of AND operations, OR operations, INVERT operations, and SHIFT operations without performing a sense line address access.

3 . The apparatus of claim 2 , wherein the sensing circuitry comprises a number of sense amplifiers and a number of compute components.

4 . The apparatus of claim 3 , wherein each one of the number of compute components comprises a number of transistors formed on pitch with memory cells corresponding to a particular one of a number of columns of memory cells.

5 . The apparatus of claim 1 , wherein the signed dividend element is of a signed first value and the signed divisor element is of a signed second value.

6 . The apparatus of claim 5 , wherein the first group of memory cells are configured to store the signed first value as a signed dividend bit-vector and the second group of memory cells are configured to store the signed second value as a signed divisor bit-vector.

7 . A method for performing signed division operations, comprising:
performing, using sensing circuitry, a signed division operation on:
a signed dividend element stored in a first group of memory cells coupled to a sense line and to a first number of access lines of a memory array; and
a divisor element stored in a second group of memory cells coupled to the sense line and to a number of second access lines of the memory array.

8 . The method of claim 7 , wherein performing the signed division operation further comprises providing a quotient element and a remainder element.

9 . The method of claim 7 , further comprising performing, in parallel with the signed division operation, an additional signed division operation on:
an additional signed dividend element stored in a third group of memory cells coupled to an additional sense line and to the first number of access lines; and an additional divisor element stored in a fourth group of memory cells coupled to the additional sense line and to the number of second access lines of the memory array.

10 . The method of claim 7 , wherein performing the additional signed division operation comprises providing an additional quotient element and an additional remainder element.

11 . An apparatus comprising:
a first group of memory cells coupled to a number of sense lines and to a number of first access lines; a second group of memory cells coupled to the number of sense lines and to a number of second access lines; and a controller configured to:
perform, by operating sensing circuitry, a plurality of signed division operations, in parallel, by dividing a plurality of signed dividend elements stored as bit-vectors in the first group of memory cells by a plurality of signed divisor elements stored as bit-vectors in the second group of memory cells, resulting in a plurality of results of the respective plurality of signed division operations being stored in a third group of memory cells coupled to a third sense line.

12 . The apparatus of claim 11 , wherein the plurality of results comprise a plurality of bit-vectors that represent at least one of a plurality of quotient elements and a plurality of remainder elements.

13 . The apparatus of claim 11 , wherein the third group of memory cells is a same group of memory cells as at least one of:
the first group of memory cells; and the second group of memory cells.

14 . The apparatus of claim 11 , wherein the controller is further configured to perform each of the plurality of signed division operations on a different element pair including corresponding elements from the plurality of signed dividend elements and the plurality of signed divisor elements.

15 . The apparatus of claim 11 , wherein the controller is further configured to cause storing of a first signed mask corresponding to the signed dividend elements in a fourth group of memory cells coupled to a first additional access line and to the number of sense lines, wherein the first signed mask indicates which of the signed dividend elements have a particular sign.

16 . The apparatus of claim 15 , wherein the controller is further configured to cause storing of: and
a second signed mask corresponding to the signed divisor elements in a fifth group of memory cells coupled to a second additional access line and to the number of sense lines, wherein the second signed mask indicates which of the signed divisor elements have the particular sign.

17 . A method for dividing signed elements comprising:
performing a plurality of signed division operations in parallel on:
a plurality (M) of signed dividend elements stored in a first group of memory cells coupled to a number of sense lines and to a number of first access lines; and
a plurality (M) of signed divisor elements stored in a second group of memory cells coupled to the number of sense lines and to a number of second access lines;
wherein the plurality of signed division operations are performed by performing a number of operations; and
storing, in parallel, a plurality of results of the signed division operations in:
a third group of memory cells coupled to the number of sense lines and to a number of third access lines; and
a fourth group of memory cells coupled to the number of sense lines and to a number of fourth access lines.

18 . The method of claim 17 , wherein performing the number of operations comprises performing at least one of a number of AND operations, OR operations, and SHIFT operations without transferring data via an input/output (I/O) line.

19 . The method of claim 17 , wherein the plurality of results include a plurality (M) of quotient elements stored in the third group of memory cells and a plurality (M) of remainder elements stored in the fourth group of memory cells.

20 . The method of claim 19 , wherein each of the M signed dividend elements and the M signed divisor elements are comprised of N bits.

21 . The method of claim 20 , wherein each of the N bits in each of the M signed dividend elements and the M signed divisor elements are associated with an index and wherein bits from corresponding elements that are associated with a common index are stored in memory cells that are coupled to a common sense line of the number of sense lines corresponding to each of the elements.

22 . The method of claim 20 , further comprising, creating a first signed mask corresponding to the M signed dividend elements that indicate which of the M signed dividend elements have a particular sign.

23 . The method of claim 22 , further comprising, creating a second signed mask corresponding to the M signed divisor elements that indicates which of the M signed divisor elements have a particular sign.

24 . The method of claim 23 , further comprising performing a masked negation on

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay

Classifications

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G06F5/01

  for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)} · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F7/535 Primary

  Dividing only · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title