Frequency divider with delay compensation

Patent metadata

Field	Value
Publication number	US-11075639-B1
Application number	US-202016880387-A
Country	US
Kind code	B1
Filing date	May 21, 2020
Priority date	May 21, 2020
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

First claim

What is claimed is:

1. A divider comprising:
an input to receive a differential signal;
two current mode logic (CML) D triggers, each CML D trigger further comprising a tail resistor, a first load resistor, and a second load resistor;
the tail resistor in each CML D trigger comprises a tail resistor FET of a first type biased with a tail resistor bias voltage, the tail resistor bias voltage controlling the tail resistor to produce a tail current that controls a common mode output in each CML D trigger to a specified voltage;
the first and second load resistors in each CML D trigger each comprising a FET of a second type biased, with a load resistor bias voltage, in a linear region of operation, the load resistor bias voltage controlling the first and second load resistors in each CML D trigger such that a self-resonant frequency (SRF) of the divider operates within a specified frequency range;
wherein
the two CML D triggers comprise a first CML D trigger and a second CML D trigger;
during normal operation a plus phase of the differential signal is used as a plus clock input and a minus phase of the differential signal is used as a minus clock input for the first CML D trigger;
during normal operation the plus phase of the differential signal is used as a minus clock input and the minus phase of the differential signal is used as a plus clock input for the second CML D trigger;
a plus output of the first CML D trigger is input to a plus data input of the second CML D trigger and a minus output of the first CML D trigger is input to a minus data input of the second CML D trigger; and
a plus output of the second CML D trigger is input to a minus data input of the first CML D trigger and a minus output of the second CML D trigger is input to a minus data input of the first D trigger;

each CML D trigger comprising:
a clock element comprising a differential pair of FETs comprising differential pair comprising a first FET of the first type and a second FET of the first type, the first FET of the first type having a gate coupled to the plus clock input, and a second FET of the first type having a gate coupled to the minus clock input, source nodes of the first and second FETs of the first type coupled to a drain of the tail resistor FET of the first type;
a pass element comprising a differential pair of FETs of the first type, the differential pair having a third FET of the first type and a fourth FET of the first type, a drain of the first FET of the first type coupled to sources of the third and fourth FETs of the first type, a gate of the third FET of the first type having a gate coupled to the plus data input and a fourth FET of the first type having a gate coupled to the minus data input;
a drain of the third FET of the first type coupled to the minus output of the CML D trigger and a drain of the fourth FET of the first type coupled to the plus output of the CML D trigger;
a drain of the second FET of the first type coupled to sources of a latch element differential pair, the latch element differential pair having a fifth FET of the first type and a sixth FET of the first type, a drain of the fifth FET of the first type coupled to the minus output of the CML D trigger and to a gate of the sixth FET of the first type;
a drain of the sixth FET of the first type coupled to the plus output of the CML D trigger and to a gate of the fifth FET of the first type; the first load resistor is coupled to the minus output of the CML D trigger and the second load resistor is coupled to the plus output of the CML D trigger;
a tail bias circuit to produce the tail resistor bias voltage for the tail resistor, the tail bias circuit comprising a voltage divider coupled between plus and minus phases of a differential output of at least one of the CML D triggers, a voltage produced by the voltage divider is coupled to a first input of an operational amplifier and a reference voltage is coupled to a second input of the operational amplifier, an output of the operational amplifier is coupled to a controller that drives the tail resistor bias voltage.

2. The divider of claim 1 wherein: all FETs of the first type are NFETs; and all FETs of the second type are PFETs.

3. The divider of claim 1 wherein: All FETs of the first type are PFETs; and All FETs of the second type are NFETs.

4. The divider of claim 1 , further comprising:
an initialization circuit to put the divider into a self-resonant mode during a calibration time, and passing the differential signal in normal mode, the initialization circuit comprising:
a first switch having a first end coupled to a plus phase of the differential signal and a second switch having a first end coupled to a minus phase of the differential signal;
a first capacitor coupled between a second end of the first switch and the plus clock input of the first CML D trigger and to the minus clock input of second CML D trigger;
a second capacitor coupled between a second end of the second switch and to the minus clock input of the first CML D trigger and to the plus clock input of the second CML D trigger; and
a resistor network to make a high impedance common mode voltage of the differential signal drive the plus clock input and the minus clock input of the first and second CML D triggers when the first and second switches are opened.

5. The divider of claim 1 further comprising:
a single counter to count cycles of the divider during a calibration time;
a high threshold coupled to the single counter to compare against the single counter value at an end of the calibration time and a low threshold coupled to the single counter to compare against the single counter value at the end of the calibration time; and
a controller to adjust a current source coupled to a resistor to generate a voltage to cause the load resistor bias voltage to make the load resistors a higher resistance when the single counter value is greater than the high threshold and to make the load resistors a lower value when the single counter value is less than the low threshold.

6. The divider of claim 5 , further comprising a buffer between the divider and the single counter.

7. The divider of claim 5 , further comprising a latch to hold the value of the single counter at the end of the calibration time to couple the single counter to the high and low thresholds.

8. The divider of claim 5 , the high threshold and the low threshold are loadable registers.

Assignees

• IBM

Inventors

• Chakraborty Sudipto
• You Yang

Classifications

• H03D13/001

  in which a pulse counter is used followed by a conversion into an analog signal · CPC title

• H03B19/14

  by means of a semiconductor device · CPC title

• H03L7/0895

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• H03L7/089 Primary

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title