Current steering phase control for CML circuits

Patent metadata

Field	Value
Publication number	US-9800249-B2
Application number	US-201615051156-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Feb 23, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first and second current-carrying branches of frequency-dividing circuitry operably connected to respective load resistors, which are connected to a power rail. A first switch element of the circuit is connected between the current sink and the first current-carrying branch and a second switch element of the circuit is connected between the current sink and the second current-carrying branch. The first and second switch elements may steer current sank by the current sink between the first and second current-carrying branches effective to alter a phase of a signal provided by the frequency division circuit.

First claim

What is claimed is:

1. A circuit for frequency division, the circuit comprising:
a first current sink or a first current source connected to a first potential;
a first current-carrying branch of frequency-dividing circuitry operably connected to a first load resistor;
a second current-carrying branch of the frequency-dividing circuitry operably connected to a second load resistor, the first and second load resistors connected to a second potential;
a first switch element connected between the current sink or the current source and the first current-carrying branch of the frequency-dividing circuitry; and
a second switch element connected between the current sink or the current source and the second current-carrying branch of the frequency-dividing circuitry;
a second current sink or a second current source connected to the first potential;
a third switch element connected between the second current sink or the second current source and the first current-carrying branch of the frequency-dividing circuitry; and
a fourth switch element connected between the second current sink or the second current source and the second current-carrying branch of the frequency-dividing circuitry.

2. The circuit as recited in claim 1 , wherein the circuit comprises the first current sink.

3. The circuit as recited in claim 2 , wherein a gate of the first switch element is connected to a gate of the fourth switch element and a gate of the second switch element is connected to a gate of the third switch element.

4. The circuit as recited in claim 1 , wherein the circuit comprises the first current source.

5. The circuit as recited in claim 1 , wherein:
the first current-carrying branch of the frequency-dividing circuitry is operably connected to the first load resistor via a switch of the frequency-dividing circuitry; and
the second current-carrying branch of the frequency-dividing circuitry is operably connected to the second load resistor via a switch of the frequency-dividing circuitry.

6. The circuit as recited in claim 1 , wherein the first potential is a ground rail and the second potential is power rail.

7. The circuit as recited in claim 1 , wherein the first potential is a power rail and the second potential is a ground rail.

8. The circuit as recited in claim 1 , wherein a gate of the first current sink or the first current source is operably connected to a local oscillator, voltage controlled oscillator, or phase-locked loop circuit.

9. The circuit as recited in claim 1 , wherein the first and second switch elements are configured to steer current sank by the first current sink or sourced by the first current source through either the first current-carrying branch or the second current-carrying branch to control a phase of a signal provided by the frequency-dividing circuitry.

10. The circuit as recited in claim 9 , wherein steering the current sank by the first current sink or sourced by the first current source through the first current-carrying branch or the second current-carrying branch is effective to shift a phase of current applied to the frequency-dividing circuitry by one-hundred and eighty (180) degrees.

11. The circuit as recited in claim 9 , wherein steering the current sank by the first current sink or sourced by the first current source through the first current-carrying branch or second current-carrying branch is effective to shift a phase of the signal provided by the frequency-dividing circuitry by ninety (90) degrees.

12. The circuit as recited in claim 1 , wherein one or more of the first current sink, first current source, switch elements, and frequency-dividing circuitry is implemented via p-type or n-type metal-oxide-semiconductor field-effect transistors (MOSFETs).

13. The circuit as recited in claim 1 , wherein the circuit is embodied as at least part of a receiver, transmitter, transceiver, clock signal generator, modulator, demodulator, signal mixer, or frequency synthesizer.

14. A frequency division circuit comprising:
first current-mode logic (CIVIL) latch circuitry having outputs connected to a first potential via a first set of resistors;
second CIVIL latch circuitry having inputs connected to the outputs of the first CML latch circuitry and outputs connected to the first potential via a second set of resistors, the outputs of the second CML latch circuitry connected to inputs of the first CIVIL latch circuitry;
a first CML clock input having a terminal connected to a second potential;
a second CIVIL clock input having a terminal connected to the second potential;
a first set of switch elements comprising a first switch element interposed between another terminal of the first CIVIL clock input and the first CML latch circuitry, and a second switch element interposed between another terminal of the second CIVIL clock input and the second CIVIL latch circuitry; and
a second set of switch elements comprising a third switch element interposed between the other terminal of the first CIVIL clock input and the second CML latch circuitry, and a fourth switch element interposed between the other terminal of the second CML clock input and the first CML latch circuitry.

15. The frequency division circuit as recited in claim 14 , wherein a gate of the first switch element is connected to a gate of the second switch element or a gate of the third switch element is connected to a gate of the fourth switch element.

16. The frequency division circuit as recited in claim 14 , wherein:
the first set of switch elements steers current sank or sourced by the first CIVIL clock input through the first CIVIL latch circuitry and current sank or sourced by the second CML clock input through the second CIVIL latch circuitry; and
the second set of switch elements steers the current sank or sourced by the first CML clock input through the second CIVIL latch circuitry and current sank or sourced by the second CML clock input through the first CML latch circuitry.

17. The frequency division circuit as recited in claim 14 , wherein the first potential is higher than the second potential.

18. The frequency division circuit as recited in claim 14 , wherein the first potential is lower than the second potential.

19. The frequency division circuit as recited in claim 14 , wherein respective gates of the first and second CML clock inputs are connected to a local oscillator from which a differential signal is received.

20. The frequency division circuit as recited in claim 19 , wherein the differential signal is a first differential signal having a first frequency, the outputs of the first CML latch circuitry provide a second differential signal having a second frequency, and the outputs of the second CIVIL latch circuitry provide a third differential signal having the second frequency.

21. The frequency division circuit as recited in claim 20 , wherein the second and third differential signals vary by approximately ninety (90) degrees.

22. The frequency division circuit as recited in claim 19 , further comprising a capacitor interposed between at least one of the respective gates of the first CML clock input or the second CML clock input and the local oscillator.

23. The frequency division circuit as recited in claim 14 , further comprising a resistor interposed between at least one of respective gates of the first CIVIL clock input or the second CIVIL clock input and a third potential.

24. A circuit for frequency division, the circuit compr

Assignees

• Qualcomm Inc

Inventors

• Rajavi Yashar
• Yang Jeongsik
• Lei Emilia Vailun

Classifications

• H03K3/0372

  of the primary-secondary type · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H03K3/3562

  of the primary-secondary type · CPC title

• H03K21/026 Primary

  comprising logic circuits · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title