Phase-locked loop with an adjustable output divider

Patent metadata

Field	Value
Publication number	US-9385769-B2
Application number	US-201414562531-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Dec 5, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

An apparatus relates generally to providing a divided signal output. In such an apparatus, a controller is coupled to receive a reference frequency count and a feedback frequency count to determine a difference therebetween to provide a control setting. A divider is coupled to receive the control setting to provide the divided signal output. The divider includes an adjustable load impedance. The control setting is coupled to adjust the load impedance of the divider to adjust a self-resonance frequency of the divider.

First claim

What is claimed is:

1. An apparatus for providing a divided signal output, comprising:
a controller configured to receive a reference frequency count and a feedback frequency count and configured to determine a difference between the reference frequency count and the feedback frequency count to provide as a control setting;
an output divider (“divider”) configured to receive the control setting and to divide the control setting to provide the divided signal output;
wherein the divider includes an adjustable load impedance; and
wherein the divider is configured to adjust load impedance of the divider responsive to the control setting to adjust a self-resonance frequency of the divider.

2. The apparatus according to claim 1 , wherein the controller comprises:
a first counter configured to receive a reference clock signal to provide the reference frequency count; and
a second counter configured to receive a feedback clock signal to provide the feedback frequency count.

3. The apparatus according to claim 2 , wherein the controller includes a finite state machine configured to receive the reference frequency count and the feedback frequency count to determine the difference in order to provide the control setting.

4. The apparatus according to claim 3 , wherein the finite state machine is configured to switch between a first calibration mode for calibration of the divider and a second calibration mode for calibration of a voltage controlled oscillator.

5. The apparatus according to claim 3 , wherein the finite state machine includes a table to store a plurality of resistance settings including a resistance setting for the load impedance of the divider.

6. The apparatus according to claim 3 , wherein the control setting is further configured to adjust a tail current of the divider.

7. The apparatus according to claim 3 , wherein the divider is an IQ divider, the apparatus further comprising:
a voltage controlled oscillator;
a multiplexer coupled to the voltage controlled oscillator and configured to select an oscillator output for input to the IQ divider;
wherein the IQ divider is a divide-by-2 IQ divider;
a first level shifter configured to receive a first quadrature clock signal output from the IQ divider; and
a second level shifter configured to receive a second quadrature clock signal output from the IQ divider.

8. The apparatus according to claim 7 , further comprising:
a feedback divider configured to receive a first level-shifted output from the first level shifter to output the feedback clock signal;
a termination node configured to receive a second level-shifted output from the second level shifter to provide a dummy load for the IQ divider;
a phase-frequency detector configured to receive the feedback clock signal and the reference clock signal to provide an internal voltage;
a loop filter configured to receive a control voltage to provide a filtered output; and
wherein the voltage controlled oscillator is configured to receive the filtered output.

9. The apparatus according to claim 8 , wherein:
the voltage controlled oscillator comprises an inductance-capacitance (“LC”) tank oscillator; and
the apparatus is an LC-quadrature phase-locked loop (“LC-QPLL”).

10. The apparatus according to claim 8 , wherein the voltage controlled oscillator comprises:
a first voltage controlled oscillator and a second voltage controlled oscillator configured to receive the filtered output to respectively provide a first oscillation signal and a second oscillation signal;
wherein the first voltage controlled oscillator is for an upper frequency range of a plurality of frequencies;
wherein the second voltage controlled oscillator is for a lower frequency range of the plurality of frequencies;
wherein the multiplexer is a first multiplexer;
wherein the first multiplexer is configured to receive the first oscillation signal and the second oscillation signal as inputs and configured to receive a first control select signal to select either the first oscillation signal or the second oscillation signal as the oscillator output; and
a second multiplexer configured to receive the internal voltage and an external voltage as inputs and configured to receive a second control select signal and configured to select either the internal voltage or the external voltage as the control voltage for input to the loop filter.

11. A method for tuning an adjustable divider, comprising:
initiating a calibration mode to cause the adjustable divider to self-resonate to obtain a feedback count;
determining a difference between a reference count and the feedback count to produce an error vector;
obtaining a control setting using the error vector; and
adjusting impedance of the adjustable divider with the control setting.

12. The method according to claim 11 , wherein the adjusting of the adjustable divider shifts a sensitivity curve thereof.

13. The method according to claim 11 , wherein the adjusting of the adjustable divider shifts a self-resonance frequency of the adjustable divider at least closer to a predetermined frequency of operation.

14. The method according to claim 11 , further comprising:
determining whether a magnitude of the error vector is greater than a threshold value;
repeating the steps of obtaining and adjusting to obtain an updated feedback count; and
repeating the step of determining with the updated feedback count to produce an updated error vector.

15. The method according to claim 11 , wherein the adjusting comprises an adjusting of an adjustable resistance of the adjustable divider.

16. The method according to claim 11 , wherein the adjusting comprises an adjusting of an adjustable capacitance of the adjustable divider.

17. The method according to claim 11 , wherein the adjusting comprises an adjusting of an adjustable tail current bias voltage of the adjustable divider.

18. The method according to claim 11 , wherein the adjusting comprises an adjusting of an adjustable resistance and an adjustable tail current bias voltage of the adjustable divider.

19. A method for adjusting an operating range in an integrated circuit die, comprising:
disabling an output of a voltage controlled oscillator of a first phase-locked loop;
sweeping codes of a first adjustable IQ divider of the first phase-locked loop;
obtaining self-resonance frequencies as outputs of the first adjustable IQ divider corresponding to the codes swept;
populating a table with the codes swept having pointers respectively thereto;
wherein the pointers are respectively associated with the self-resonance frequencies; and
selecting a code of the codes swept for a predetermined operating frequency to adjust a second adjustable IQ divider in a second phase-locked loop in the integrated circuit die.

20. The method according to claim 19 , wherein the selecting of the code comprises storing the code for use with the second adjustable IQ divider.

Assignees

• Xilinx Inc

Inventors

• Elzeftawi Mohamed N

Classifications

• H03D7/1441

  using field-effect transistors (H03D7/145 takes precedence) · CPC title

• H03L7/183

  a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} · CPC title

• H04B1/163 Primary

  Special arrangements for the reduction of the damping of resonant circuits of receivers (amplifiers H03F; negative impedance networks for line transmission systems H04B3/16) · CPC title

• H04B1/0483 Primary

  Transmitters with multiple parallel paths · CPC title

• H03B19/12 Primary

  using division only · CPC title