Current mode logic circuit with multiple frequency modes

Patent metadata

Field	Value
Publication number	US-9281810-B2
Application number	US-201414276644-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	May 13, 2014
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

First claim

What is claimed is:

1. A device, comprising:
a clock circuit to provide a first differential clock signal;
a control circuit to generate a control signal based at least in part on a frequency of the first differential clock signal; and
a current mode logic (CML) circuit, including a pair of differential transistors, to generate a second differential clock signal based at least in part on the first differential clock signal and to operate in one of a plurality of different frequency modes based at least in part on the control signal.

2. The device of claim 1 , wherein:
the CML circuit includes a number of variable resistors coupled to the pair of differential transistors and responsive to the control signal; and
the CML circuit includes a variable current source coupled to the pair of differential transistors and responsive to the control signal.

3. The device of claim 2 , wherein a relatively low value of the control signal denotes a relatively low value of the frequency and is to set a relatively high resistance value for the variable resistors, and a relatively high value of the control signal denotes a relatively high value of the frequency and is to set a relatively low resistance value for the variable resistors.

4. The device of claim 2 , wherein a relatively low value of the control signal denotes a relatively low value of the frequency and is to select a relatively low bias current for the variable current source, and a relatively high value of the control signal denotes a relatively high value of the frequency and is to select a relatively high bias current for the variable current source.

5. The device of claim 2 , further comprising:
a memory including a plurality of entries corresponding to the plurality of different frequency modes, wherein each entry stores a resistance value of the variable resistors for a corresponding range of frequencies of the first differential clock signal.

6. The device of claim 5 , wherein each entry of the memory stores a bias current value for the variable current source for the corresponding range of frequencies of the first differential clock signal.

7. The device of claim 6 , wherein at least one of the ranges comprises a specific frequency value.

8. The device of claim 5 , wherein the control circuit is to generate the control signal by accessing the memory.

9. A current mode logic (CML) circuit to generate an output differential clock signal based at least in part on an input differential clock signal, the CML circuit comprising:
a variable current source coupled to a first voltage supply and including a control terminal to receive a control signal denoting a frequency of the input differential clock signal;
a pair of transistors coupled to the variable current source and responsive to the input differential clock signal; and
a pair of variable resistors coupled between the pair of transistors and a second voltage supply, wherein each of the variable resistors includes a control terminal to receive the control signal,
wherein the CML circuit is coupled to a control circuit, the control circuit to generate the control signal based at least in part on the frequency of the input differential clock signal.

10. The CML circuit of claim 9 , wherein the CML circuit is to operate in a selected one of a plurality of different frequency modes based at least in part on the control signal.

11. The CML circuit of claim 9 , wherein the control circuit is coupled to a memory including a plurality of entries corresponding to a plurality of different frequency modes, wherein each entry stores a selected resistance value of the variable resistors for a corresponding range of frequencies of the input differential clock signal.

12. The CML circuit of claim 9 , wherein the control circuit is coupled to a memory including a plurality of entries corresponding to a plurality of different frequency modes, wherein each entry stores a selected bias current value for the variable current source for a corresponding range of frequencies of the input differential clock signal.

13. In a device comprising a current mode logic (CML) circuit including a differential transistor pair coupled to a number of variable resistors and to a variable current source, a method comprising:
determining a frequency of an input differential clock signal;
generating a control signal based at least in part on the determined frequency;
selecting one of a plurality of different frequency modes based at least in part on the control signal; and
generating an output differential clock signal based at least in part on the input differential clock signal.

14. The method of claim 13 , wherein the selecting comprises:
selecting one of a plurality of resistance values for the variable resistors; and
selecting one of a plurality of bias current values for the variable current source.

15. The method of claim 14 , wherein selecting the resistance value and selecting the bias current value comprises:
accessing a memory including a plurality of entries, each entry storing a selected resistance value and a selected bias current value for a corresponding one of the plurality of different frequency modes.

16. The method of claim 13 , wherein the selecting comprises:
providing the determined frequency to a memory including a plurality of entries each storing a resistance value for a corresponding range of frequencies;
selecting one of the resistance values based at least in part on the determined frequency;
embodying the selected resistance value into the control signal; and
setting at least one of the variable resistors to the selected resistance value.

17. The method of claim 13 , wherein the selecting comprises:
providing the determined frequency to a memory including a plurality of entries each storing a bias current value for a corresponding range of frequencies;
selecting one of the bias current values based at least in part on the determined frequency;
embodying the selected bias current value into the control signal; and
setting the variable current source to provide the selected bias current.

18. The method of claim 13 , wherein a relatively low value of the control signal denotes a relatively low value of the determined frequency and selects a relatively high resistance value for the variable resistors, and a relatively high value of the control signal denotes a relatively high value of the determined frequency and selects a relatively low resistance value for the variable resistors.

19. The method of claim 13 , wherein a relatively low value of the control signal denotes a relatively low value of the determined frequency and selects a relatively high bias current value for the variable current source, and a relatively high value of the control signal denotes a relatively high value of the determined frequency and selects a relatively low bias current value for the variable current source.

Assignees

• Qualcomm Inc

Inventors

• Singh Guneet
• Cranford Jr Hayden Clavie
• Fertsch Michael Thomas

Classifications

• H03K5/01 Primary

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• H03K19/018514

  with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence) · CPC title

• H03K19/09432

  with coupled sources or source coupled logic (H03K19/096 takes precedence) · CPC title