Methods for forming structures for MRAM applications

Patent metadata

Field	Value
Publication number	US-11069853-B2
Application number	US-201816195313-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Nov 19, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

First claim

What is claimed is:

1. An interconnection structure comprising:
at least three magnetic tunnel junction structures disposed on a substrate, a first magnetic tunnel junction structure of the at least three magnetic tunnel junction structures comprising:
a first ferromagnetic layer;
a second ferromagnetic layer disposed on and contacting a top surface of a first lower interconnection structure, wherein the first ferromagnetic layer and the second ferromagnetic layer sandwich a tunneling barrier layer; and
a hardmask layer disposed on the first ferromagnetic layer;

a spin orbit torque (SOT) layer having a bottommost surface disposed on and contacting a top surface of the hardmask layer, wherein the SOT layer is electrically conductive; and
two or more back end structures disposed on the SOT layer, wherein a number of the two or more back end structures is less than a number of the at least three magnetic tunnel junction structures.

2. The interconnection structure of claim 1 , wherein the hardmask layer is formed from a material that is the same as the SOT layer.

3. The interconnection structure of claim 2 , wherein the material of the hardmask layer is CoFeB, MgO, Ta, W, Pt, CuBi, Mo and Ru.

4. The interconnection structure of claim 1 , wherein at least one of the two or more back end structures is a dual damascene structure.

5. The interconnection structure of claim 1 ,
wherein the first lower interconnection structure is formed under the first magnetic tunnel junction structure.

6. The interconnection structure of claim 1 , wherein the SOT layer connects at least one of the two or more back end structures to the first lower interconnection structure through the first magnetic tunnel junction structure.

7. The interconnection structure of claim 1 , wherein at least one of the two or more back end structures is connected to a second lower interconnection structure.

8. The interconnection structure of claim 1 , wherein three of the at least three magnetic tunnel junction structures are connected to the SOT layer.

9. The interconnection structure of claim 1 , wherein the first magnetic tunnel junction structure further comprises:
a seed layer formed on a bottom of the first magnetic tunnel junction structure.

10. The interconnection structure of claim 1 , wherein the hardmask layer is a capping layer.

11. The interconnection structure of claim 1 , wherein a width of the SOT layer is larger than a width of the hardmask layer.

12. The interconnection structure of claim 1 , wherein at least one of the two or more back end structures is disposed outside an edge of the first magnetic tunnel junction structure.

13. The interconnection structure of claim 1 , wherein the SOT layer is configured to electrically couple at least one of the two or more back end structures with the first magnetic tunnel junction structure.

14. The interconnection structure of claim 7 , wherein the first magnetic tunnel junction structure is disposed in a layer between the two or more back end structures and the second lower interconnection structure.

Assignees

• Applied Materials Inc

Inventors

• Tseng Hsin-Wei
• Park Chando
• Ahn Jaesoo
• Xue Lin
• Pakala Mahendra

Classifications

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H01L43/02

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic