Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11069706-B2
Application number	US-201916573695-A
Country	US
Kind code	B2
Filing date	Sep 17, 2019
Priority date	Dec 12, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
a stack structure disposed on the substrate and comprising a plurality of electrodes and first insulating layers disposed between the electrodes, the stack structure having a stair structure on the connection region;
a vertical channel structure penetrating the stack structure on the cell array region; and
a vertical dummy structure penetrating at least a portion of the stair structure on the connection region,
wherein the stack structure further comprises: a second insulating layer selectively disposed on the cell array region and not disposed on the connection region,
wherein a maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer,
wherein the vertical channel structure includes a portion of abrupt diameter change at a level of a top surface of the second insulating layer,
wherein the portion of abrupt diameter change has: a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer, and
wherein an upper portion of the portion of abrupt diameter change has a first diameter, and a lower portion of the portion of abrupt diameter change has a second diameter that is greater than the first diameter.

2. The 3D semiconductor memory device of claim 1 , wherein a first electrode of the plurality of electrodes extends from a sidewall of the second insulating layer onto the connection region.

3. The 3D semiconductor memory device of claim 2 , wherein the first electrode has a first thickness, and
wherein a second electrode of the electrodes has a second thickness that is greater than the first thickness.

4. The 3D semiconductor memory device of claim 1 , wherein a portion of the vertical dummy structure at the level of the top surface of the second insulating layer has a third diameter at its upper portion and has a fourth diameter at its lower portion, and wherein the fourth diameter is smaller than the third diameter.

5. The 3D semiconductor memory device of claim 1 , wherein a sidewall of the vertical channel structure has a stepped profile at a level of the portion of abrupt diameter change.

6. The 3D semiconductor memory device of claim 5 , wherein a sidewall of the vertical dummy structure has a flat profile at the level of the portion of abrupt diameter change.

7. The 3D semiconductor memory device of claim 1 , wherein the vertical channel structure and the vertical dummy structure include different layers.

8. The 3D semiconductor memory device of claim 1 , wherein the vertical channel structure and the vertical dummy structure include the same layers.

9. The 3D semiconductor memory device of claim 1 , wherein the vertical dummy structure comprises a lower dummy structure and an upper dummy structure, and
wherein the upper dummy structure at least partially overlaps the lower dummy structure in a cross-sectional view.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kang-Won
• Song Jaeyoung
• Lee Dong-Sik
• Jang Donghoon

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H10B12/485 Primary

  Bit line contacts · CPC title