Horizontal nanosheet FETs and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10026652-B2
Application number	US-201615343157-A
Country	US
Kind code	B2
Filing date	Nov 3, 2016
Priority date	Aug 17, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

First claim

What is claimed is:

1. An integrated circuit comprising a plurality of horizontal nanosheet (hNS) devices on a top surface of a substrate, the plurality of hNS devices comprising a first hNS device and a second hNS device spaced apart from each other in a lateral direction of the integrated circuit,
wherein each of the hNS devices comprises a plurality of horizontal nanosheets spaced apart in a thickness direction of the integrated circuit, the plurality of horizontal nanosheets comprising a first horizontal nanosheet and a second horizontal nanosheet; and
a gate stack between the first and the second horizontal nanosheets, the gate stack comprising a work function metal (WFM) layer,
wherein a thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and
a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

2. The integrated circuit of claim 1 , wherein each of the hNS devices further comprises a third horizontal nanosheet spaced apart from the first and second horizontal nanosheets in the thickness direction of the integrated circuit; and
a gate stack between the second and the third horizontal nanosheets.

3. The integrated circuit of claim 1 , wherein a work function metal of the WFM layer of the first hNS device is the same as a work function metal of the WFM layer of the second hNS device.

4. The integrated circuit of claim 1 , wherein the thickness of the first and second horizontal nanosheets of the first hNS device is thinner than the thickness of the first and second horizontal nanosheets of the second hNS device, and
the thickness of the WFM layer of the first hNS device is thicker than the thickness of the WFM layer of the second hNS device.

5. The integrated circuit of claim 1 , wherein a threshold voltage (Vt) of the first hNS device is different from a threshold voltage (Vt) of the second hNS device.

6. The integrated circuit of claim 1 , wherein the WFM layer comprises a reactive work function metal.

7. The integrated circuit of claim 6 , wherein the reactive work function metal is Ti, Al, Zr, La, Hf, TiAlC, or a combination thereof.

8. The integrated circuit of claim 1 , wherein the WFM layer comprises a mid-gap work function metal.

9. The integrated circuit of claim 8 , wherein the mid-gap work function metal is TiN, TaN, TiTaSiN, or a combination thereof.

10. The integrated circuit of claim 9 , wherein the WFM layer further comprises a reactive work function metal.

11. The integrated circuit of claim 1 , further comprising a third and a fourth hNS devices, wherein a threshold voltage of the first hNS device, a threshold voltage of the second hNS device, a threshold voltage of the third hNS device, and a threshold voltage of the fourth hNS device are different from one another.

12. The integrated circuit of claim 11 , wherein the thickness of the WFM layer of the first hNS device, the thickness of the WFM layer of the second hNS device, a thickness of the WFM layer of the third hNS device, and a thickness of the WFM layer of the fourth hNS device are different from one another.

13. The integrated circuit of claim 1 , wherein the WFM layer of each of the first and second hNS devices is a single continuous layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark S
• Obradovic Borna J
• Hong Joon Goo

Classifications

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L21/823412

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic