Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Patent metadata

Field	Value
Publication number	US-9905643-B1
Application number	US-201615248237-A
Country	US
Kind code	B1
Filing date	Aug 26, 2016
Priority date	Aug 26, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

First claim

What is claimed is:

1. A semiconductor structure comprising at least:
a substrate;
at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;
a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;
a source region;
a drain region;
a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; and
a second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the drain region.

2. The semiconductor structure of claim 1 , wherein a thickness of each semiconductor layer in the alternating stack is between 3 nm and 60 nm.

3. The semiconductor structure of claim 1 , wherein the alternating stack is disposed in contact with the substrate.

4. The semiconductor structure of claim 1 , further comprising:
a first dielectric layer formed on and in contact with a top surface of the source region; and
a second dielectric layer formed on and in contact with a top surface of the drain region.

5. The semiconductor structure of claim 4 , further comprising:
a first spacer disposed between and in contact with the metal gate and the first dielectric layer, the first spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the first plurality of epitaxially grown interconnects; and
a second spacer disposed between and in contact with the metal gate and the second dielectric layer, the second spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the second plurality of epitaxially grown interconnects.

6. The semiconductor structure of claim 1 , wherein the epitaxially grown interconnect material contacts sidewall portions of the source region between the first plurality of epitaxially grown interconnects.

7. The semiconductor structure of claim 6 , wherein the epitaxially grown interconnect material contacts sidewall portions of the drain region between the first plurality of epitaxially grown interconnects.

8. The semiconductor structure of claim 1 , further comprising a cap layer in contact with the metal gate.

9. The semiconductor structure of claim 1 , wherein each epitaxially grown interconnect of the first plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith, and wherein each epitaxially grown interconnect of the second plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith.

10. An integrated circuit comprising:
a semiconductor structure comprising at least:
a substrate;
at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;
a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;
a source region;
a drain region;
a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; and
a second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the drain region.

11. The integrated circuit of claim 10 , wherein a thickness of each semiconductor layer in the alternating stack is between 3 nm and 60 nm.

12. The integrated circuit of claim 10 , wherein the alternating stack is disposed in contact with the substrate.

13. The integrated circuit of claim 10 , wherein the semiconductor structure further comprises:
a first dielectric layer formed on and in contact with a top surface of the source region; and
a second dielectric layer formed on and in contact with a top surface of the drain region.

14. The integrated circuit of claim 13 , wherein the semiconductor structure further comprises:
a first spacer disposed between and in contact with the metal gate and the first dielectric layer, the first spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the first plurality of epitaxially grown interconnects; and
a second spacer disposed between and in contact with the metal gate and the second dielectric layer, the second spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the second plurality of epitaxially grown interconnects.

15. The integrated circuit of claim 10 , wherein the epitaxially grown interconnect material contacts sidewall portions of the source region between the first plurality of epitaxially grown interconnects.

16. The integrated circuit of claim 15 , wherein the epitaxially grown interconnect material contacts sidewall portions of the drain region between the first plurality of epitaxially grown interconnects.

17. The integrated circuit of claim 10 , wherein the semiconductor structure further comprises a cap layer in contact with the metal gate.

18. The integrated circuit of claim 10 , wherein each epitaxially grown interconnect of the first plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith, and wherein each epitaxially grown interconnect of the second plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith.

Assignees

• IBM

Inventors

• Bergendahl Marc A
• Cheng Kangguo
• Miller Eric R
• Sporre John R
• Teehan Sean

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L21/76895

  Electricity · mapped topic

• H01L29/0673 Primary

  Electricity · mapped topic