Wafer Level optoelectronic device packages and methods for making the same

Patent metadata

Field	Value
Publication number	US-9305967-B1
Application number	US-201514749169-A
Country	US
Kind code	B1
Filing date	Jun 24, 2015
Priority date	Apr 16, 2015
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Described herein are methods for fabricating a plurality of optoelectronic devices, and the optoelectronic devices resulting from such methods. One such method includes performing through silicon via (TSV) processing on a wafer, which includes a plurality of light detector sensor regions, to thereby form a plurality of vias, and then tenting and plating the vias and performing wafer back metallization. Thereafter, plurality of light source dies are attached to a top surface of the wafer, and a light transmissive material is then molded to encapsulate the light detector sensor regions and the light sensor dies therein. Additionally, opaque barriers including opaque optical crosstalk barriers are fabricated. Further, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is eventually diced to separate the wafer into a plurality of optoelectronic devices.

First claim

What is claimed is:

1. A method for fabricating a plurality of optoelectronic devices, comprising:
(a) performing through silicon via (TSV) processing on a wafer, which includes a plurality of light detector sensor regions, to thereby form a plurality of vias;
(b) tenting and plating the vias and performing wafer back metallization, after performing the TSV processing;
(c) attaching each of a plurality of light source dies to a top surface of the wafer; and
(d) molding a light transmissive material to encapsulate the light detector sensor regions and the light sensor dies in the light transmissive material, after the (b) tenting and plating the vias and performing wafer back metallization, and after the (c) attaching the plurality of light source dies to the top surface of the wafer;
(e) fabricating opaque barriers including opaque optical crosstalk barriers;
(f) attaching solder balls or other electrical connectors to the bottom of the wafer; and
(g) dicing the wafer to separate the wafer into a plurality of optoelectronic devices.

2. The method of claim 1 , further comprising:
before the (a) performing TSV processing on the wafer, backgrinding a bottom of the wafer, which includes the plurality of light detector sensor regions, to achieve a specified thickness for the wafer.

3. The method of claim 2 , wherein the (a) performing TSV processing on the wafer comprises performing bottom-up TSV processing on the wafer, after the backgrinding the bottom of the wafer.

4. The method of claim 3 , wherein the (a) performing through silicon via (TSV) processing on the wafer, and the (b) tenting and plating the vias and performing wafer back metallization, are both performed before the (c) attaching the plurality of light source dies to the top surface of the wafer, and before the (d) molding the light transmissive material to encapsulate the light detector sensor regions and the light sensor dies in the light transmissive material.

5. The method of claim 2 , wherein the (c) attaching the plurality of light source dies to the top surface of the wafer, is performed after the performing the backgrinding, after the (a) performing the TSV processing on the wafer, and after the (b) tenting and plating the vias and the performing wafer back metallization.

6. The method of claim 1 , wherein the (f) attaching solder balls or other electrical connectors to the bottom of the wafer is performed before the (d) molding the light transmissive material to encapsulate the light detector sensor regions and the light sensor dies in the light transmissive material.

7. The method of claim 1 , wherein the (f) attaching solder balls or other electrical connectors to the bottom of the wafer is performed after the (d) molding the light transmissive material to encapsulate the light detector sensor regions and the light sensor dies in the light transmissive material.

8. The method of claim 1 , wherein each of the optoelectronic devices, resulting from the (g) dicing the wafer, includes at least one of the light detector sensor regions, at least one of the light source dies, one of the opaque optical crosstalk barriers between the at least one of the light detector sensor regions and the at least one of the light source dies, and at least two of the solder balls or other electrical connectors.

9. The method of claim 1 , wherein the (e) fabricating opaque barriers also includes fabricating opaque specular reflection reducing shelves and opaque peripheral barriers.

10. The method of claim 9 , wherein the fabricating the opaque optical crosstalk barriers, the specular reflection reducing shelves and the opaque peripheral barriers comprises molding an opaque material to produce the opaque optical crosstalk barriers, the specular reflection reducing shelves and the opaque peripheral barriers.

11. The method of claim 10 , wherein the molding the light transmissive material, and the molding the opaque material to produce the opaque optical crosstalk barriers, the opaque specular reflection reducing shelves and the opaque peripheral barriers, are performed using a dual molding process.

12. The method of claim 9 , wherein the fabricating opaque optical crosstalk barriers, the opaque specular reflection reducing shelves and peripheral barriers, comprises attaching preformed opaque optical crosstalk barriers, specular reflection reducing shelves and peripheral barriers to the wafer.

13. The method of claim 1 , wherein each of the light detector sensor regions comprises a CMOS image sensor fabricated using CMOS device fabrication.

14. A method for fabricating a plurality of optoelectronic devices, comprising:
(a) forming a plurality of light detector sensor regions in a top surface of a wafer;
(b) after forming the plurality of light detector sensor regions in the top surface of the wafer, forming a plurality of vias in the wafer;
(c) after forming the plurality of vias in the wafer, tenting and plating the vias and performing wafer back metallization;
(d) after tenting and plating the vias and performing wafer back metallization, attaching a plurality of light source dies to the top surface of the wafer such that each of the light source dies is spaced apart from one of the light detector sensor regions;
(e) after attaching the plurality of light source dies to the top surface of the wafer, encapsulating the plurality of light detector sensor regions and the plurality of light source dies in a light transmissive molding material;
(f) attaching solder balls or other electrical connectors to the bottom of the wafer; and
(g) separating the wafer into a plurality of optoelectronic devices.

15. The method of claim 14 , wherein each of the light detector sensor regions comprises a CMOS image sensor fabricated using CMOS device fabrication.

16. The method of claim 14 , further comprising, prior to separating the wafer into the plurality of optoelectronic devices, attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, the preformed opaque structure including opaque vertical optical barriers.

17. The method of claim 16 , wherein the preformed opaque structure made-off wafer is made from one or more etched sheets of opaque material, or is molded off-wafer.

18. The method of claim 14 , further comprising, prior to separating the wafer into the plurality of optoelectronic devices, forming opaque optical crosstalk barriers on-wafer.

19. The method of claim 14 , wherein the (f) attaching solder balls or other electrical connectors to the bottom of the wafer occurs at any time after the tenting and plating the vias and performing wafer back metallization, and prior to the separating the wafer into the plurality of optoelectronic devices.

20. A method for fabricating a plurality of optoelectronic devices, comprising:
(a) forming a plurality of light detector sensor regions in a top surface of a wafer;
(b) backgrinding a bottom of the wafer, which includes the plurality of light detector sensor regions, to achieve a specified thickness for the wafer;
(c) performing bottom-up through silicon via (TSV) processing on the wafer, after the backgrinding the bottom of the wafer;
(d) tenting and plating the vias and performing wafer back metallization, after performing the bottom-up TSV processing;
(e) attaching each of a plurality of light source dies to a top surface of the wafer, after the tenting and plating the vias and performing wafer back metallization;
(f) molding a light transmissive material to encapsulate the light detecto

Assignees

• Intersil Americas LLC

Inventors

• A Tharumalingam Sri Ganesh

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• G01V8/12 Primary

  using one transmitter and one receiver · CPC title