Wafer-level fan-out package with enhanced performance

Patent metadata

Field	Value
Publication number	US-11069590-B2
Application number	US-201916454687-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Oct 10, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.

First claim

What is claimed is:

1. An apparatus comprising:
a first thinned die comprising a first device layer, a first dielectric layer over the first device layer, and a plurality of first die bumps underneath the first device layer;
a second die comprising a second device layer, a silicon substrate over the second device layer, and a plurality of second die bumps underneath the second device layer;
a multilayer redistribution structure formed underneath the first thinned die and the second die;
a first mold compound residing over the silicon substrate of the second die;
a second mold compound residing over the multilayer redistribution structure, around and underneath the first thinned die, and around and underneath the second die; wherein:
the second mold compound extends beyond a top surface of the first thinned die to define an opening within the second mold compound and over the first thinned die, such that the top surface of the first thinned die is at a bottom of the opening; and
a top surface of the first mold compound and a top surface of the second mold compound are coplanar; and

a third mold compound filling the opening and in contact with the top surface of the first thinned die, wherein the first mold compound, the second mold compound, and the third mold compound are formed from different materials.

2. The apparatus of claim 1 wherein the multilayer redistribution structure comprises a plurality of package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnections that connect the plurality of package contacts to certain ones of the plurality of first die bumps and certain ones of the plurality of second die bumps.

3. The apparatus of claim 2 wherein:
the redistribution interconnections electrically connect the first thinned die and the second die; and
the first thinned die provides a microelectromechanical system (MEMS) component and the second die provides a complementary metal-oxide-semiconductor (CMOS) controller that controls the MEMS component.

4. The apparatus of claim 2 wherein:
the multilayer redistribution structure is glass-free;
connections between the redistribution interconnections and the plurality of first die bumps are solder-free; and
connections between the redistribution interconnections and the plurality of second die bumps are solder-free.

5. The apparatus of claim 1 wherein the first thinned die is formed from a silicon-on-insulator (SOI) structure, wherein the first device layer of the first thinned die is formed from a silicon layer of the SOI structure, and the first dielectric layer of the first thinned die is a buried oxide layer of the SOI structure.

6. The apparatus of claim 1 wherein the third mold compound has an electrical resistivity greater that 1E6 Ohm-cm.

7. The apparatus of claim 1 wherein the third mold compound has a thermal conductivity greater than 2 W/m·K.

8. The apparatus of claim 1 wherein the third mold compound has a thermal conductivity greater than 10 W/m·K.

9. The apparatus of claim 1 wherein the top surface of the first thinned die at the bottom of the opening is a top surface of the first dielectric layer.

10. The apparatus of claim 1 wherein a portion of the third mold compound resides over the first mold compound and the second mold compound.

11. The apparatus of claim 1 wherein the top surface of the first mold compound, the top surface of the second mold compound, and a top surface of the third mold compound are coplanar.

12. The apparatus of claim 1 wherein a periphery of the first mold compound and a periphery of the silicon substrate of the second die are coincident.

13. An apparatus comprising:
a first thinned die comprising a first device layer, a first dielectric layer over the first device layer, and a plurality of first die bumps underneath the first device layer;
a second die comprising a second device layer, a silicon substrate over the second device layer, and a plurality of second die bumps underneath the second device layer;
a multilayer redistribution structure formed underneath the first thinned die and the second die;
a first mold compound residing over the silicon substrate of the second die;
a second mold compound residing over the multilayer redistribution structure, around and underneath the first thinned die, and around and underneath the second die; wherein:
the second mold compound extends beyond a top surface of the first thinned die to define an opening within the second mold compound and over the first thinned die, such that the top surface of the first thinned die is at a bottom of the opening; and
a top surface of the first mold compound and a top surface of the second mold compound are coplanar;

a third mold compound filling the opening and in contact with the top surface of the first thinned die, wherein the top surface of the first mold compound, the top surface of the second mold compound, and a top surface of the third mold compound are coplanar; and
a fourth mold compound, which resides over the top surface of the first mold compound, the top surface of the second mold compound, and the top surface of the third mold compound.

14. The apparatus of claim 13 wherein the first mold compound, the second mold compound, and the fourth mold compound are formed from a same material.

15. A method comprising:
providing a precursor package that includes a first die, a second die, a first mold compound, and a second mold compound, wherein:
the first die comprises a first device layer, a first dielectric layer over the first device layer, a first silicon substrate over the first dielectric layer, and a plurality of first die bumps underneath the first device layer;
the second die comprises a second device layer, a second silicon substrate over the second device layer, and a plurality of second die bumps underneath the second device layer;
the first mold compound resides over the second silicon substrate of the second die; and
the second mold compound resides around and underneath the first die and the second die; such that the second mold compound partially covers sidewalls of the first die, covers a bottom surface of the first die, covers sidewalls and a bottom surface of the second die, partially covers sidewalls of the first mold compound, and encapsulates the first die bumps and the second die bumps, wherein the first mold compound and the first silicon substrate extend vertically beyond a top surface of the second mold compound;

planarizing a top surface of the precursor package to provide a mold package, such that a top surface of the first mold compound, the top surface of the second mold compound, and a backside of the first silicon substrate are coplanar;
removing substantially the first silicon substrate to provide a first thinned die and form an opening within the second mold compound and over the first thinned die, wherein the first thinned die has a top surface exposed at a bottom of the opening; and
applying a third mold compound to substantially fill the opening and directly contact the top surface of the first thinned die.

16. The method of claim 15 further comprising:
thinning the second mold compound to expose each of the plurality of first die bumps and each of the plurality of second die bumps; and
forming a multilayer redistribution structure underneath the second mold compound, wherein the multilayer redistribution structure comprises a plurality of package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnections that connect the plurality of pac

Assignees

• Qorvo Us Inc

Inventors

• Hammond Jonathan Hale
• Costa Julio C
• Chadwick Jon

Classifications

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title