Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Semiconductor device package and method
US8941248B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941248-B2 |
| Application number | US-201313800383-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.
First claim
Opening claim text (preview).
What is claimed is: 1. A package comprising: a substrate; a chip electrically and mechanically attached to a surface of the substrate by electrical connectors; and a hybrid encapsulant encapsulating the chip, the hybrid encapsulant comprising a first molding compound and a second molding compound, the first molding compound being on the surface of the substrate and around a periphery of the chip, the second molding compound being on the first molding compound and around the pe…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8941248B2 cover?
- Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a ch…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W74/012. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).