Integrated clock gating circuit

Patent metadata

Field	Value
Publication number	US-11063592-B2
Application number	US-202016991659-A
Country	US
Kind code	B2
Filing date	Aug 12, 2020
Priority date	Nov 12, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

An integrated circuit gating circuit includes a first control stage that outputs a first internal signal based on an enable signal and a clock signal, a second control stage that outputs a second internal signal based on the first internal signal and the clock signal, and an output driver that outputs an output clock signal based on the second internal signal. The second control stage includes a first multi-finger transistor that is connected between a second node outputting the second internal signal and the 0-th node and operates based on the clock signal. A first portion of the first multi-finger transistor is formed in a first row defined on a semiconductor substrate, and a second portion of the first multi-finger transistor is formed in a second row defined on the semiconductor substrate.

First claim

What is claimed is:

1. An integrated circuit gating circuit comprising:
a first control stage configured to output a first internal signal based on an enable signal and a clock signal;
a second control stage connected to the first control stage through a first node, and configured to output a second internal signal based on the first internal signal and the clock signal; and
an output driver configured to output an output clock signal based on the second internal signal,
wherein the second control stage includes a first multi-finger transistor connected between a second node outputting the second internal signal and the first node, and configured to operate based on the clock signal, and
wherein a first portion of the first multi-finger transistor is formed in a first row on a semiconductor substrate between a first power line and a second power line, and a second portion of the first multi-finger transistor is formed in a second row on the semiconductor substrate between the second power line and a third power line.

2. The integrated circuit gating circuit of claim 1 , wherein the first portion of the first multi-finger transistor and the second portion of the first multi-finger transistor share at least one first gate line, and
wherein the at least one first gate line is extended along a first direction from the first row to the second row and the clock signal is provided to the at least one gate line.

3. The integrated circuit gating circuit of claim 2 ,
wherein the first portion of the first multi-finger transistor further comprises first source areas and first drain areas,
wherein the second portion of the first multi-finger transistor further comprises second source areas and second drain areas,
wherein the first source areas and the second source areas are electrically interconnected through first intermediate contacts,
wherein the first drain areas of the first portion of the first multi-finger transistor and the second drain areas of the second portion of the first multi-finger transistor are electrically interconnected through second intermediate contacts, and
wherein the first intermediate contacts and the second intermediate contacts are formed to be closer to the semiconductor substrate than a metal layer formed on the semiconductor substrate.

4. The integrated circuit gating circuit of claim 2 ,
wherein the first portion of the first multi-finger transistor further comprises first source areas and first drain areas,
wherein the second portion of the first multi-finger transistor further comprises second source areas and second drain areas,
wherein the first source areas of the first portion of the first multi-finger transistor and the second source areas of the second portion of the first multi-finger transistor are electrically interconnected through first metal lines, and
wherein the first drain areas of the first portion of the first multi-finger transistor and the second drain areas of the second portion of the first multi-finger transistor are electrically interconnected through second metal lines.

5. The integrated circuit gating circuit of claim 1 , wherein the first control stage includes:
second and third multi-finger transistors connected in series between the first node and a ground,
wherein the second multi-finger transistor operates based on the enable signal, a third portion of the second multi-finger transistor is formed in the first row, and a fourth portion of the second multi-finger transistor is formed in the second row, and
wherein the third multi-finger transistor operates based on the first internal signal, a fifth portion of the third multi-finger transistor is formed in the first row, and a sixth portion of the third multi-finger transistor is formed in the second row.

6. The integrated circuit gating circuit of claim 5 , wherein the third portion formed in the first row and the fourth portion formed in the second row share at least one second gate line to which the enable signal is provided,
wherein the fifth formed in the first row and the sixth portion formed in the second row share at least one third gate line to which the first internal signal is provided, and
wherein the at least one second gate line and the at least one third gate line are extended along a first direction from the first row to the second row.

7. The integrated circuit gating circuit of claim 1 , wherein the second control stage further includes a feedback inverter configured to invert the second internal signal and to output an inverted second internal signal, and
wherein the feedback inverter is formed in the second row.

8. The integrated circuit gating circuit of claim 7 , wherein the first control stage is further configured to control a voltage level at the first node based on the inverted second internal signal, the enable signal, and the first internal signal.

9. The integrated circuit gating circuit of claim 1 , wherein a power supply voltage is provided to the first power line and the third power line, and a ground voltage is provided to the second power line.

10. The integrated circuit gating circuit of claim 9 , wherein the first portion of the first multi-finger transistor is formed in the first row and in a first area adjacent to the second power line, and
wherein the second portion of the first multi-finger transistor is formed in the second row and in a second area adjacent to the second power line.

11. The integrated circuit gating circuit of claim 1 , wherein the output driver includes at least one second multi-finger transistor,
wherein a third portion of the at least one second multi-finger transistor is formed in the first row, and a fourth portion of the at least one second multi-finger transistor is formed in the second row,
wherein the third portion of the second multi-finger transistor and the fourth portion of the second multi-finger transistor share at least one second gate line, and
wherein the second internal signal is provided to the at least one gate line.

12. An integrated circuit gating circuit comprising:
a clock signal control circuit configured to output a first internal signal based on a clock signal and a voltage level at a first node;
an enable signal control circuit configured to operate based on the first internal signal, an enable signal, and an inverted second internal signal;
an output control circuit connected to the first node, and configured to output a second internal signal based on the clock signal and the first internal signal;
a feedback inverter configured to invert the second internal signal and output the inverted second internal signal; and
an output driver configured to output an output clock signal based on the second internal signal,
wherein the clock signal control circuit is provided in a first row of a semiconductor substrate,
wherein the enable signal control circuit is distributed and arranged in the first row and a second row of the semiconductor substrate,
wherein the output control circuit is distributed and arranged at the first row and the second row,
wherein the feedback inverter is provided at the second row, and
wherein the output driver is distributed and arranged at the first row and the second row.

13. The integrated circuit gating circuit of claim 12 , wherein the first row corresponds to a first area of the semiconductor substrate between a first power line and a second power line, and the second row corresponds to a second area of the semiconductor substrate between the second power line and a third power line.

14. The integrated circuit gating circuit of claim 12 , wherein the enable signal control circ

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Youngo
• Kim Ahreum
• Kim Minsu

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title