Clock gating circuit

Patent metadata

Field	Value
Publication number	US-10355674-B2
Application number	US-201715658214-A
Country	US
Kind code	B2
Filing date	Jul 24, 2017
Priority date	Jul 24, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first stage that receives an enable signal and provides a first intermediate signal based on the enable signal;
a second stage that receives the first intermediate signal, an input clock signal, and an inverted input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal, the input clock signal, and the inverted input clock signal; and
a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

2. The integrated circuit of claim 1 , wherein the first stage comprises a logic function circuit having a NOR gate structure that provides the first intermediate signal based on the enable signal and the input clock signal.

3. The integrated circuit of claim 1 , wherein the second stage comprises a latching function circuit for holding a data value through use of the ternary logic response to the first intermediate signal and the input clock signal.

4. The integrated circuit of claim 1 , wherein the second stage comprises a latching function circuit having a ternary logic structure that provides the ternary logic response to the first intermediate signal and the input clock signal.

5. The integrated circuit of claim 4 , wherein the ternary logic structure of the second stage comprises less than four transistors arranged to receive the first intermediate signal and the input clock signal and provide the second intermediate signal based on the ternary logic response to the first intermediate signal and the input clock signal.

6. The integrated circuit of claim 5 , wherein the less than four transistors of the ternary logic structure of the second stage comprises complementary metal-oxide-semiconductor (CMOS) transistors including two P-type MOS (PMOS) transistors and one N-type MOS (NMOS) transistor.

7. The integrated circuit of claim 1 , wherein the third stage comprises a logic function circuit having a NAND gate structure and an inverter gate structure arranged to provide the output clock signal based on the second intermediate signal and the input clock signal.

8. The integrated circuit of claim 1 , wherein the third stage comprises an integrated clock gating circuit that interrupts the input clock signal to a logical off state in response to the second intermediate signal and the input clock signal.

9. The integrated circuit of claim 1 , wherein the third stage provides a feedback signal to the second stage, and wherein the second stage receives the feedback signal and provides the second intermediate signal based on the ternary logic response to the first intermediate signal, the input clock signal and the feedback signal.

10. The integrated circuit of claim 9 , wherein the feedback signal comprises an inverted clock signal.

11. The integrated circuit of claim 9 , wherein the third stage comprises:
a NAND gate structure that receives the second intermediate signal and the input clock signal and provides the feedback signal based on the second intermediate signal and the input clock signal; and
an inverter gate structure coupled to the NAND gate structure, wherein the inverter gate structure receives the feedback signal from the NAND gate structure and provides the output clock signal based on the feedback signal.

12. An integrated circuit, comprising:
logic function circuitry that provides a first intermediate signal based on receiving an enable signal;
latching function circuitry that receives the first intermediate signal, an input clock signal, and an inverted input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal, the input clock signal, and the inverted input clock signal; and
integrated clock gating circuitry that receives the second intermediate signal and the input clock signal, interrupts the input clock signal to a logical off state, and provides an output clock signal in response to receiving the second intermediate signal and the input clock signal.

13. The integrated circuit of claim 12 , wherein the logic function circuitry comprises a NOR gate structure that provides the first intermediate signal based on the enable signal and the input clock signal.

14. The integrated circuit of claim 12 , wherein the latching function circuitry holds a data value through use of the ternary logic response to the first intermediate signal and the input clock signal.

15. The integrated circuit of claim 12 , wherein the latching function circuitry comprises less than four transistors arranged to receive the first intermediate signal and the input clock signal and provide the second intermediate signal based on the ternary logic response to the first intermediate signal and the input clock signal.

16. The integrated circuit of claim 12 , wherein the integrated clock gating circuitry comprises a NAND gate structure and an inverter gate structure arranged to provide the output clock signal based on the second intermediate signal and the input clock signal.

17. The integrated circuit of claim 12 , wherein the integrated clock gating circuitry further provides a feedback signal to the latching function circuitry, and wherein the latching function circuitry receives the feedback signal and provides the second intermediate signal based on the ternary logic response to the first intermediate signal, the input clock signal and the feedback signal.

18. The integrated circuit of claim 17 , wherein the feedback signal comprises an inverted clock signal.

19. The integrated circuit of claim 17 , wherein the integrated clock gating circuitry comprises:
a NAND gate structure that receives the second intermediate signal and the input clock signal and provides the feedback signal based on the second intermediate signal and the input clock signal; and
an inverter gate structure coupled to the NAND gate structure, wherein the inverter gate structure receives the feedback signal from the NAND gate structure and provides the output clock signal based on the feedback signal.

20. A method for manufacturing an integrated circuit, the method comprising:
fabricating a first stage to receive an enable signal and to provide a first intermediate signal based on the enable signal;
fabricating a second stage to receive the first intermediate signal, an input clock signal, and an inverted input clock signal and to provide a second intermediate signal based on a ternary logic response to the first intermediate signal, the input clock signal, and the inverted input clock signal; and
fabricating a third stage to receive the second intermediate signal and the input clock signal and provide an output clock signal based on the second intermediate signal and the input clock signal.

21. The integrated circuit of claim 3 , wherein the latching function circuit for holding the data value is additionally responsive to the inverted input clock signal and wherein a first ternary circuit establishes the first intermediate signal, wherein a second ternary circuit provides a portion of the latching function, and wherein an output of the second ternary circuit is shared with an output signal from the first ternary circuit.

22. The integrated circuit of claim 4 , wherein the latching function circuit for holding a data value through use of the ternary logic is additionally in response to the inverted clock si

Assignees

• Advanced Risc Mach Ltd

Inventors

• Baratam Anil Kumar
• Prabhu Nruthya Nagesh
• Laplanche Yves Thomas

Classifications

• H03K3/356121 Primary

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title