Integrated clock gate circuit with embedded NOR

Patent metadata

Field	Value
Publication number	US-10177765-B2
Application number	US-201615244839-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Aug 23, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

First claim

We claim:

1. An apparatus comprising:
an AND-OR-INVERT (AOI) static latch coupled to a clock node, test node, and enable node, wherein the AOI static latch has embedded NOR logic;
a NAND gate having a first input coupled to the clock node and a second input coupled to an output of the AOI static latch; and
an inverter coupled to an output of the NAND gate, wherein the inverter is to provide an output, wherein the AOI static latch comprises:
a first device of a first conductivity type, wherein the first device includes a gate terminal coupled to the test node and a source terminal coupled to a power supply rail;
a second device of the first conductivity type, wherein the second device is coupled in series with the first device, wherein the second device has a gate terminal coupled to the enable node;
a third device of the first conductivity type coupled to the second device, wherein the third device has a gate terminal coupled to the clock node;
a fourth device of the first conductivity type, wherein the fourth device is coupled to the third device such that a drain terminal of the fourth device is coupled to a drain terminal of the third device;
a fifth device of a second conductivity type, the fifth device having a gate terminal coupled to the test node, and a drain terminal coupled to the drain terminals of the third and fourth devices;
a sixth device of the second conductivity type, the sixth device coupled in series with the third device and coupled in parallel to the fifth device, wherein the sixth device has a gate terminal coupled to the enable node;
a seventh device of the second conductivity type, wherein the seventh device is coupled in parallel to the sixth device, wherein the seventh device has a gate terminal coupled to the clock node; and
an eighth device of the second conductivity type, wherein the eighth device is coupled in series with the fifth, sixth, and seventh devices, wherein the eighth device has a gate terminal coupled to a gate terminal of the fourth device.

2. The apparatus of claim 1 comprises a NOR gate having a first input coupled to the test node and a second input coupled to the enable node.

3. The apparatus of claim 2 , wherein the AOI static latch with embedded NOR logic comprises a ninth device of the first conductivity type, the ninth device having a source terminal coupled to the power supply rail, and a gate terminal coupled to an output of the NOR gate.

4. The apparatus of claim 3 , wherein the AOI static latch with embedded NOR logic comprises a tenth device of the first conductivity type, the tenth device coupled in series with the ninth device.

5. The apparatus of claim 4 , wherein the AOI static latch with embedded NOR logic comprises an eleventh device of the first conductivity type, the eleventh device having a gate terminal coupled to the drain terminal of the fourth device, a drain terminal coupled to the tenth device and the gate terminals of the fourth device and the eighth device, and a source terminal coupled to the power supply rail.

6. The apparatus of claim 5 , wherein the AOI static latch with embedded NOR logic comprises:
a twelfth device of the second conductivity type, the twelfth device coupled in series with the eleventh, wherein the twelfth device has a gate terminal coupled to the clock node; and
a thirteenth device of the second conductivity type, the thirteenth device coupled in parallel with the twelfth device, wherein the thirteenth device has a gate terminal coupled to the output of the NOR gate.

7. The apparatus of claim 6 , wherein the AOI static latch with embedded NOR logic comprises a fourteenth device of the second conductivity type, the fourteenth device coupled in series with the twelfth device, wherein the fourteenth device has a gate terminal coupled to the gate terminal of the eleventh device.

8. An apparatus comprising:
a critical timing path having a pass-gate based integrated clock gate; and
a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR logic, wherein the AOI integrated clock gate comprises:
a first device of a first conductivity type, wherein the first device includes a gate terminal coupled to a test node and a source terminal coupled to a power supply rail;
a second device of the first conductivity type, wherein the second device is coupled in series with the first device, wherein the second device has a gate terminal coupled to an enable node;
a third device of the first conductivity type coupled to the second device, wherein the third device has a gate terminal coupled to a clock node;
a fourth device of the first conductivity type, wherein the fourth device is coupled to the third device such that a drain terminal of the fourth device is coupled to a drain terminal of the third device;
a fifth device of a second conductivity type, the fifth device having a gate terminal coupled to the test node, and a drain terminal coupled to the drain terminals of the third and fourth devices;
a sixth device of the second conductivity type, the sixth device coupled in series with the third device and coupled in parallel to the fifth device, wherein the sixth device has a gate terminal coupled to the enable node;
a seventh device of the second conductivity type, wherein the seventh device is coupled in parallel to the sixth device, wherein the seventh device having a gate terminal coupled to the clock node; and
an eighth device of the second conductivity type, wherein the eighth device is coupled in series with the fifth, sixth, and seventh devices, wherein the eighth device has a gate terminal coupled to a gate terminal of the fourth device.

9. The apparatus of claim 8 , wherein the pass-gate based integrated clock gate comprises:
a first inverter having an input coupled to a clock node;
a pass-gate having a first transistor of the first conductivity type with a gate terminal coupled to the clock node, and a second transistor of the second conductivity type, wherein the second transistor having a gate terminal coupled to an output of the first inverter;
a NOR gate having a first input coupled to a test node, a second input coupled to an enable node, and an output node coupled to the pass-gate;
a memory device comprising of two cross-coupled inverting structures which are coupled to the pass-gate; and
a NAND gate having a first input coupled to the clock node and a second input coupled to an output of the pass-gate via a second inverter.

10. The apparatus of claim 9 , wherein the AOI based integrated clock gate with embedded NOR logic comprises:
a NAND gate having a first input coupled to the clock node and a second input coupled to an output of the AOI static latch with embedded NOR logic.

11. A system comprising:
a memory; and
a processor coupled to the memory, the processor including:
an AND-OR-INVERT (AOI) static latch coupled to a clock node, test node, and enable node, wherein the AOI static latch has embedded NOR logic which comprises:
a first inverter coupled to an output of the AOI static latch;
a NAND gate having a first input coupled to the clock node and a second input coupled to an output of the first inverter; and
a second inverter coupled to an output of the NAND gate, wherein the second inverter is to provide an output;
a first device of a first conductivity type, wherein the first device includes a gate terminal coupled to a test node and a source terminal coupled to a power supply rail;
a second device of the first conductivity type, wherein the second device is coupled in series with the first device, wherein the second

Assignees

• Intel Corp

Inventors

• Hsu Steven K
• Agarwal Amit
• Rajwani Iqbal R
• REALOV Simeon
• Krishnamurthy Ram K

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/0944 Primary

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title