Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11063057-B2
Application number	US-201816152605-A
Country	US
Kind code	B2
Filing date	Oct 5, 2018
Priority date	Apr 30, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
a substrate;
an electrode structure on the substrate, the electrode structure including a plurality of gate electrodes sequentially stacked in a first direction, the first direction extending perpendicular to an upper surface of the substrate;
a source conductive pattern between the substrate and the electrode structure;
a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern; and
a data storage pattern extending in the first direction, the data storage pattern between the vertical semiconductor pattern and the electrode structure,
wherein a lower surface of the data storage pattern contacts the source conductive pattern, and
wherein a first portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of a second portion of the lower surface of the data storage pattern from the upper surface of the substrate.

2. The device of claim 1 , wherein
the data storage pattern includes
a first insulation pattern between the vertical semiconductor pattern and the electrode structure, and
a second insulation pattern between the first insulation pattern and the electrode structure, and

a lower surface of the first insulation pattern is at a different height from the upper surface of the substrate, in relation to a height of a lower surface of the second insulation pattern from the upper surface of the substrate.

3. The device of claim 2 , wherein the lower surface of the second insulation pattern is distal from the upper surface of the substrate, in relation to the lower surface of the first insulation pattern.

4. The device of claim 2 , wherein the lower surface of the second insulation pattern is proximate to the upper surface of the substrate, in relation to the lower surface of the first insulation pattern.

5. The device of claim 2 , wherein the lower surface of the first insulation pattern and the lower surface of the second insulation pattern contact the source conductive pattern.

6. The device of claim 2 , wherein
the data storage pattern further includes a third insulation pattern between the first insulation pattern and the vertical semiconductor pattern, and
the lower surface of the first insulation pattern is at a different height from the upper surface of the substrate, in relation to a height of a lower surface of the third insulation pattern from the upper surface of the substrate.

7. The device of claim 6 , wherein
the lower surface of the second insulation pattern is distal from the upper surface of the substrate in relation to the lower surface of the first insulation pattern, and
the lower surface of the third insulation pattern is positioned proximate to the upper surface of the substrate in relation to the lower surface of the first insulation pattern.

8. The device of claim 6 , wherein
the lower surface of the second insulation pattern is proximate to the upper surface of the substrate in relation to the lower surface of the first insulation pattern, and
the lower surface of the third insulation pattern is distal from the upper surface of the substrate in relation to the lower surface of the first insulation pattern.

9. The device of claim 6 , wherein the lower surface of the first insulation pattern is proximate to the upper surface of the substrate in relation to both the lower surface of the second insulation pattern and the lower surface of the third insulation pattern.

10. The device of claim 6 , wherein the lower surface of the first insulation pattern, the lower surface of the second insulation pattern, and the lower surface of the third insulation pattern each contact the source conductive pattern.

11. The device of claim 1 , wherein
the electrode structure extends in a second direction parallel to the upper surface of the substrate,
the source conductive pattern includes:
a horizontal portion extending in the second direction on the substrate, and
a vertical portion extending in the first direction from the horizontal portion and covering a portion of a sidewall of the vertical semiconductor pattern, and

the lower surface of the data storage pattern contacts the vertical portion of the source conductive pattern.

12. The device of claim 11 , wherein the lower surface of the data storage pattern is distal from the upper surface of the substrate in relation to an upper surface of the horizontal portion of the source conductive pattern and is proximate to the upper surface of the substrate in relation to a lower surface of a lowermost gate electrode of the plurality of gate electrodes.

13. The device of claim 11 , further comprising:
a dummy data storage pattern between the vertical semiconductor pattern and the substrate,
wherein the dummy data storage pattern is isolated from direct contact with the data storage pattern in the first direction with the source conductive pattern therebetween, and
wherein an uppermost surface of the dummy data storage pattern contacts the vertical portion of the source conductive pattern.

14. The device of claim 13 , wherein the uppermost surface of the dummy data storage pattern is lower than is the upper surface of the substrate.

15. The device of claim 14 , wherein the dummy data storage pattern and the data storage pattern include a same material.

16. The device of claim 1 , wherein
the source conductive pattern includes
a first source conductive pattern between the substrate and the electrode structure, and
a second source conductive pattern between the first source conductive pattern and the electrode structure,

wherein the first source conductive pattern and the second source conductive pattern each include a semiconductor material doped with an impurity of a first conductivity-type,
wherein a concentration of the impurity in the first source conductive pattern is different from a concentration of the impurity in the second source conductive pattern, and
wherein the lower surface of the data storage pattern contacts the first source conductive pattern.

17. The device of claim 1 , further comprising:
a common source plug penetrating the electrode structure and isolated from direct contact with the vertical semiconductor pattern,
wherein the common source plug is connected to the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• JUNG Euntaek
• Shin Joongshik
• Shin Dongyoun

Classifications

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic