Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices

Patent metadata

Field	Value
Publication number	US-11062960-B2
Application number	US-201916599723-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	Aug 17, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.

First claim

We claim:

1. A semiconductor device comprising:
a first field-effect transistor device and a second field-effect transistor device disposed on a substrate, wherein the first field-effect transistor device comprises a first source/drain layer, and wherein the second field-effect transistor device comprises a second source/drain layer;
a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench;
wherein the shared contact trench comprises:
a first silicide contact layer disposed on the first source/drain layer of the first field-effect transistor device;
a second silicide contact layer disposed on the second source/drain layer of the second field-effect transistor device, wherein the first and second silicide contact layers comprise different silicide materials; and
a metallic fill layer disposed on the first and second silicide contact layers.

2. The semiconductor device of claim 1 , wherein the first and second field-effect transistor devices comprise n-type and p-type fin field-effect transistor devices.

3. The semiconductor device of claim 2 , wherein the first and second source/drain layers are disposed on adjacent vertical semiconductor fins of the first and second field-effect transistor devices.

4. The semiconductor device of claim 1 , wherein one of the first and second silicide contact layers comprises titanium silicide, and wherein the other of the first and second silicide contact layers comprises one of nickel silicide, a platinum silicide, nickel-platinum silicide, and cobalt silicide.

5. The semiconductor device of claim 1 , wherein the metallic fill material comprises at least one of tungsten, ruthenium, cobalt, and copper.

6. The semiconductor device of claim 1 , wherein the first and second source/drain layers comprise epitaxial layers.

7. The semiconductor device of claim 6 , wherein at least one of the first source/drain layer and the second source/drain layer comprises a silicon-germanium epitaxial material.

8. The semiconductor device of claim 6 , wherein at least one of the first source/drain layer and the second source/drain layer comprises a silicon-phosphorus epitaxial material.

9. The semiconductor device of claim 1 , wherein:
the first silicide contact layer comprises a first metal-semiconductor alloy layer that is formed by combining a first epitaxial semiconductor contact layer and a first metallic contact layer through a thermal annealing process, wherein the first epitaxial semiconductor contact layer is epitaxially grown on the first source/drain layer and wherein the first metallic contact layer is deposited on the first epitaxial semiconductor contact layer; and
the second silicide contact layer comprises a second metal-semiconductor alloy layer that is formed by combining a second epitaxial semiconductor contact layer and a second metallic contact layer through the thermal annealing process, wherein the second epitaxial semiconductor contact layer is epitaxially grown on the second source/drain layer and wherein the second metallic contact layer is deposited on the second epitaxial semiconductor contact layer.

10. The semiconductor device of claim 9 , wherein the first epitaxial semiconductor contact layer comprises a boron-doped silicon germanium epitaxial material, and wherein the first metallic contact layer comprises one of nickel platinum and cobalt.

11. The semiconductor device of claim 9 , wherein the second epitaxial semiconductor contact layer comprises one of a silicon phosphorous epitaxial material and a silicon arsenide epitaxial material, and wherein the second contact layer comprises one of titanium and titanium nitride.

12. The semiconductor device of claim 1 , further comprising an insulating capping layer disposed on the metallic fill layer.

13. A semiconductor device comprising:
a shared contact trench comprising a first source/drain layer and a second source/drain layer, wherein the first and second source/drain layers are commonly connected to each other by the shared contact trench;
wherein the shared contact trench comprises:
a first silicide contact layer disposed on the first source/drain layer;
a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials; and
a metallic fill layer disposed on the first and second silicide contact layers.

14. The semiconductor device of claim 13 , wherein the first and second source/drain layers are disposed on adjacent vertical semiconductor fins of first and second field-effect transistor devices.

15. The semiconductor device of claim 13 , wherein one of the first and second silicide contact layers comprises titanium silicide, and wherein the other of the first and second silicide contact layers comprises one of nickel silicide, a platinum silicide, nickel-platinum silicide, and cobalt silicide.

16. The semiconductor device of claim 13 , wherein the metallic fill material comprises at least one of tungsten, ruthenium, cobalt, and copper.

17. The semiconductor device of claim 13 , wherein the first and second source/drain layers comprise epitaxial layers.

18. The semiconductor device of claim 17 , wherein:
the first source/drain layer comprises a silicon-germanium epitaxial material; and
the second source/drain layer comprises one of a silicon-phosphorus epitaxial material and a silicon arsenide epitaxial material.

19. The semiconductor device of claim 13 , wherein:
the first silicide contact layer comprises a first metal-semiconductor alloy layer that is formed by combining a first epitaxial semiconductor contact layer and a first metallic contact layer through a thermal annealing process, wherein the first epitaxial semiconductor contact layer is epitaxially grown on the first source/drain layer and wherein the first metallic contact layer is deposited on the first epitaxial semiconductor contact layer; and
the second silicide contact layer comprises a second metal-semiconductor alloy layer that is formed by combining a second epitaxial semiconductor contact layer and a second metallic contact layer through the thermal annealing process, wherein the second epitaxial semiconductor contact layer is epitaxially grown on the second source/drain layer and wherein the second metallic contact layer is deposited on the second epitaxial semiconductor contact layer.

20. The semiconductor device of claim 19 , wherein:
the first epitaxial semiconductor contact layer comprises a boron-doped silicon germanium epitaxial material, and wherein the first metallic contact layer comprises one of nickel platinum and cobalt; and
the second epitaxial semiconductor contact layer comprises one of a silicon phosphorous epitaxial material and a silicon arsenide epitaxial material, and wherein the second contact layer comprises one of titanium and titanium nitride.

Assignees

• IBM

Inventors

• Wu Heng
• Cheng Kangguo
• Wang Junli
• Liu Zuoguang

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/3444

  P-type · CPC title