Integrated circuits with dual silicide contacts and methods for fabricating same

Patent metadata

Field	Value
Publication number	US-9293462-B2
Application number	US-201414167778-A
Country	US
Kind code	B2
Filing date	Jan 29, 2014
Priority date	Jan 29, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate having a selected source/drain region and a non-selected source/drain region;
forming a contact resistance modulation material over the selected source/drain region;
depositing a dielectric material over the selected source/drain region and the non-selected source/drain region;
etching the dielectric material to form a first trench exposing the selected source/drain region and to form a second trench exposing the non-selected source/drain region;
forming a metal layer in the first trench over the selected source/drain region and in the second trench over the non-selected source/drain region;
filling the first trench and the second trench with a contact metal to form a first contact structure over the selected source/drain region and a second contact structure over the non-selected source/drain region, wherein a portion of the dielectric material isolates the first contact structure from the second contact structure; and
annealing the metal layer to form silicide contacts on the selected source/drain region and the non-selected source/drain region.

2. The method of claim 1 wherein forming a contact resistance modulation material over the selected source/drain region comprises growing epitaxial material on the selected source/drain region.

3. The method of claim 1 wherein forming a contact resistance modulation material over the selected source/drain region comprises epitaxially growing germanium on the selected source/drain region.

4. The method of claim 1 wherein the non-selected source/drain region comprise phosphorus-doped silicon, wherein the selected source/drain region comprise silicon germanium, and wherein forming a contact resistance modulation material over the selected source/drain region comprises epitaxially growing germanium on the selected source/drain region.

5. The method of claim 1 further comprising masking the non-selected source/drain region before forming the contact resistance modulation material over the selected source/drain region.

6. The method of claim 5 further comprising:
unmasking the non-selected source/drain region after forming the contact resistance modulation material over the selected source/drain region and before forming the metal layer in the first trench over the selected source/drain region and in the second trench over the non-selected source/drain region.

7. The method of claim 5 further comprising:
unmasking the non-selected source/drain region after forming the contact resistance modulation material over the selected source/drain region and before forming the metal layer in the first trench over the selected source/drain region and in the second trench over the non-selected source/drain region; and
filling the first trench and the second trench with the contact metal after forming the metal layer in the first trench over the selected and in the second trench over the non-selected source/drain region and before annealing the metal layer to form silicide contacts on the selected source/drain region and the non-selected source/drain region.

8. The method of claim 1 wherein the method further comprises:
depositing the dielectric material over the selected source/drain region and the non-selected source/drain region after forming the contact resistance modulation material over the selected source/drain regions; and
masking the non-selected source/drain region before forming the contact resistance modulation material over the selected source/drain region.

9. The method of claim 1 wherein providing a semiconductor substrate having the selected source/drain region and the non-selected source/drain region comprises forming fin structures overlying the semiconductor substrate, wherein the selected source/drain region and the non-selected source/drain region are located in the fin structures.

10. The method of claim 1 wherein forming the metal layer in the first trench over the selected source/drain region and in the second trench over the non-selected source/drain region comprises depositing a continuous metal layer extending from over the selected source/drain region to over the non-selected source/drain region.

11. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate having a selected source/drain region and a non-selected source/drain region;
depositing a dielectric material over the selected source/drain region and the non-selected source/drain region;
etching the dielectric material to form a trench exposing the selected source/drain region and the non-selected source/drain region;
selectively forming a contact resistance modulation material over the selected source/drain region;
depositing a continuous metal layer extending from over the selected source/drain region to over the non-selected source/drain region;
annealing the continuous metal layer to form silicide contacts on the selected source/drain region and the non-selected source/drain region; and
filling the trench with a contact metal to form a contact structure in electrical contact with the selected source/drain region and the non-selected source/drain region and extending from over the selected source/drain region to over the non-selected source/drain region.

12. The method of claim 11 wherein the trench is formed with sidewalls and wherein depositing the continuous metal layer comprises depositing the continuous metal layer on the sidewalls.

13. The method of claim 11 wherein filling the trench with the contact metal comprises depositing the contact metal onto the continuous metal layer extending from over the selected source/drain region to over the non-selected source/drain region.

14. The method of claim 11 wherein selectively forming the contact resistance modulation material over the selected source/drain region comprises forming a mask in the trench over the non-selected source/drain region before forming the contact resistance modulation material over the selected source/drain region.

15. The method of claim 14 further comprising:
unmasking the non-selected source/drain region after forming the contact resistance modulation material over the selected source/drain region and before depositing the continuous metal layer extending from over the selected source/drain region to over the non-selected source/drain region; and
filling the trench with the contact metal after depositing the continuous metal layer extending from over the selected source/drain region to over the non-selected source/drain region and before annealing the continuous metal layer to form silicide contacts on the selected source/drain region and the non-selected source/drain region.

Assignees

• Globalfoundries Inc

Inventors

• Koh Shao Ming
• Bouche Guillaume
• Wahl Jeremy A
• Wei Andy C

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title