Chained split execution of fused compound arithmetic operations

Patent metadata

Field	Value
Publication number	US-11061672-B2
Application number	US-201615202351-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Oct 2, 2015
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

A microprocessor is configured for unchained and chained modes of split execution of a fused compound arithmetic operation. In both modes of split execution, a first execution unit executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and a second instruction execution unit receives the intermediate result and executes a second part of the fused compound arithmetic operation to produce a final result. In the unchained mode, execution is accomplished by dispatching separate split-execution microinstructions to the first and second instruction execution units. In the chained mode, execution is accomplished by dispatching a single split-execution microinstruction to the first instruction execution unit and sending a chaining control signal or signal group to the second execution unit, causing it to execute its part of the fused arithmetic operation without needing an instruction.

First claim

The invention claimed is:

1. A microprocessor comprising:
first and second instruction execution units, each instruction execution unit comprising a characteristic set of logic circuitry provided to execute any of a designated set of microinstructions of a first type delivered to it for completion, and to produce final results thereof;
a plurality of dispatch ports, each coupled to a corresponding one of the first and second instruction execution units; and
a scheduler, determining to which one of the dispatch ports a microinstruction is bound, and the clock cycle during which the microinstruction is dispatched;
wherein the first and second instruction execution units are also configured to perform chained and non-chained modes of split execution of a fused compound arithmetic operation, one in which the first instruction execution unit, after receiving a split-execution microinstruction, executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and in which the second instruction execution unit receives the intermediate result and executes a second part of the fused compound arithmetic operation to produce a final result;
wherein in the non-chained mode of split execution, first and second non-chained split-execution microinstructions are issued by the scheduler to the first and second instruction execution units, respectively, to execute the first part and the second part of the fused compound arithmetic operation;
wherein in the chained mode of split execution, a single chained split-execution microinstruction is issued by the scheduler to the first instruction execution unit to execute the first part of the fused compound arithmetic operation, and no corresponding microinstruction is issued by the scheduler to the second instruction execution unit, wherein the second instruction execution unit starts to execute the second part of the fused compound arithmetic operation after receiving the intermediate result from the first instruction execution unit, wherein the scheduler reserves the second instruction execution unit for executing the second part of the fused compound arithmetic operation by not dispatching a microinstruction through the dispatch port corresponding to the second instruction execution unit, and wherein when the second instruction execution unit detects that the single chained split-execution microinstruction is issued to the first instruction execution unit, the second instruction execution unit sets a flag that causes it to begin executing the fused compound arithmetic operation at the proper clock cycle.

2. The microprocessor of claim 1 , further comprising a configurable signal source that stores a configuration setting to specify the mode of split execution.

3. The microprocessor of claim 2 , wherein the microprocessor is configured to issue either the first and second non-chained split-execution microinstructions, or the single chained split-execution microinstruction, in accordance with the configuration setting, in response to an instruction specifying the compound arithmetic operation.

4. The microprocessor of claim 2 , further comprising a translator configured to translate an instruction specifying the compound arithmetic operation in accordance with the configuration setting into either the first and second non-chained split-execution microinstructions for performing the non-chained mode of split execution, or into a single chained split-execution microinstruction for performing the chained mode of split execution.

5. The microprocessor of claim 2 , wherein the configuration setting is configured to be set by supervisory software.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Elmer Thomas
• Patil Nikhil A

Classifications

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F7/575

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/223

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title