Systolic array with input reduction to multiple reduced inputs
US-2026023529-A1 · Jan 22, 2026 · US
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Elmer Thomas patents
Elmer Thomas is listed as an inventor on 54 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Elmer Thomas |
| Total patents | 54 |
| First publication | Aug 11, 2015 |
| Latest publication | Jan 22, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Systolic array with output rounding for multiple source/destination data type pairs
US-12517700-B1 · Jan 6, 2026 · US
Significand shifting in floating point processing operations
US-12423097-B2 · Sep 23, 2025 · US
Systolic array with input reduction to multiple reduced inputs
US-12423058-B2 · Sep 23, 2025 · US
Logic gate complexity
US-2025274127-A1 · Aug 28, 2025 · US
Logic gate complexity
US-2025272464-A1 · Aug 28, 2025 · US
Floating point accumulation
US-2025244951-A1 · Jul 31, 2025 · US
Significand shifting in floating point processing operations
US-2025245004-A1 · Jul 31, 2025 · US
Increasing performance of computational array accelerators
US-12182691-B1 · Dec 31, 2024 · US
Multiple accumulate busses in a systolic array
US-12182064-B2 · Dec 31, 2024 · US
Recent patents
Latest publications not already listed above.
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US-2024361986-A1 · Oct 31, 2024 · US
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US-12067375-B2 · Aug 20, 2024 · US
Systolic array with efficient input reduction and extended array performance
US-11880682-B2 · Jan 23, 2024 · US
Systolic multiply delayed accumulate processor architecture
US-11842169-B1 · Dec 12, 2023 · US
Multiple accumulate busses in a systolic array
US-2023385233-A1 · Nov 30, 2023 · US
Systolic array component combining multiple integer and floating-point data types
US-11816446-B2 · Nov 14, 2023 · US
Multiple accumulate busses in a systolic array
US-11762803-B2 · Sep 19, 2023 · US
Triple adder
US-2023266942-A1 · Aug 24, 2023 · US
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US-2023010054-A1 · Jan 12, 2023 · US
Systolic array with input reduction to multiple reduced inputs
US-2023004523-A1 · Jan 5, 2023 · US
Systolic array with efficient input reduction and extended array performance
US-2023004384-A1 · Jan 5, 2023 · US
Multiple accumulate busses in a systolic array
US-2022350775-A1 · Nov 3, 2022 · US
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US-11467806-B2 · Oct 11, 2022 · US
Configurable function approximation based on switching mapping table content
US-11423313-B1 · Aug 23, 2022 · US
Multiple busses within a systolic array processing element
US-11422773-B1 · Aug 23, 2022 · US
Multiple accumulate busses in a systolic array
US-11308027-B1 · Apr 19, 2022 · US
Multiple busses interleaved in a systolic array
US-11308026-B1 · Apr 19, 2022 · US
Parallelism within a systolic array using multiple accumulate busses
US-11232062-B1 · Jan 25, 2022 · US
Chained split execution of fused compound arithmetic operations
US-11061672-B2 · Jul 13, 2021 · US
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US-2021157548-A1 · May 27, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Amazon Tech Inc | 29 |
| Via Alliance Semiconductor Co Ltd | 25 |
| Advanced Risc Mach Ltd | 6 |
| Uchicago Argonne Llc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F7/5443 | 44 |
| G06F9/3001 | 29 |
| G06F7/483 | 27 |
| G06F9/30014 | 24 |
| G06F9/3893 | 23 |