Calculation control indicator cache

Patent metadata

Field	Value
Publication number	US-2016004665-A1
Application number	US-201514748924-A
Country	US
Kind code	A1
Filing date	Jun 24, 2015
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A microprocessor comprises an instruction execution unit operable to generate an intermediate result vector and a plurality of calculation control indicators and storage external to the instruction execution unit which stores the intermediate result vector and the plurality of calculation control indicators. The intermediate result vector is generated from an application of at least a first arithmetic operation of a compound arithmetic operation. The calculation control indicators indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The subsequent calculations may involve one or more remaining arithmetic operations of the compound arithmetic operation. The intermediate result vector, in combination with the plurality of calculation control indicators, provides sufficient information to generate a result indistinguishable from an infinitely precise calculation of the compound arithmetic operation whose result is reduced in significance to a target data size.

First claim

1 . A microprocessor comprising:
an instruction execution unit operable to perform a portion of an arithmetic calculation to generate an intermediate result vector and to concomitantly generate a plurality of calculation control indicators as a function of generating the intermediate result vector; wherein the calculation control indicators indicate how subsequent calculations to complete the arithmetic calculation should proceed; and storage external to the instruction execution unit configured to store the intermediate result vector and the plurality of calculation control indicators.

2 . The microprocessor of claim 1 , wherein the storage comprises a general purpose storage and a calculation control indicator storage, the microprocessor further comprising:
a result bus for conveying results from the instruction execution unit to the general purpose storage; and a data path for storing and loading calculation control indicators to and from the calculation control indicator storage; wherein the result bus is separate from the data path, the general purpose storage is accessible by most instructions of an instruction set of the microprocessor to store instruction results, and the calculation control indicator storage is accessible only to instructions operable to store or load a calculation control indicator.

3 . The microprocessor of claim 1 , wherein the instruction execution unit is an arithmetic processing unit configured with three or more operand inputs and the intermediate result vector is generated from an application of a first arithmetic operation of a compound arithmetic operation to at least two of the operand inputs.

4 . The microprocessor of claim 3 , wherein the plurality of calculation control indicators indicate how a second arithmetic operation of the compound arithmetic operation, using a second arithmetic operator of a compound arithmetic operation, should proceed.

5 . The microprocessor of claim 3 , wherein the arithmetic operators are fundamental arithmetic operators, selected from the group consisting of add, subtract, multiply, and divide.

6 . The microprocessor of claim 3 , wherein the compound arithmetic operation is a sequential arithmetic operation.

7 . The microprocessor of claim 3 , wherein the compound arithmetic operation is a multiply-accumulate operation, the first arithmetic operation is at least a multiply of a multiplicand operand with a multiplier operand.

8 . The microprocessor of claim 3 , wherein the calculation control indicators provide information regarding how much of the compound arithmetic operation has been completed in generating the intermediate result vector.

9 . The microprocessor of claim 3 , wherein the calculation control indicators provide information regarding whether the first arithmetic operation resulted in an underflow or overflow condition.

10 . The microprocessor of claim 3 , wherein the intermediate result vector, considered in isolation from the calculation control indicators, is represented with fewer bits than necessary to consistently generate an arithmetically correct representation of the compound arithmetic operation; but wherein the intermediate result vector, in combination with the plurality of calculation control indicators, provide sufficient information to generate an arithmetically correct representation of the compound arithmetic operation; wherein an arithmetically correct representation of the compound arithmetic operation is indistinguishable from a result that would be generated by an infinitely precise calculation of the compound arithmetic operation subsequently reduced in significance to a target data size.

11 . The microprocessor of claim 1 , wherein the intermediate result vector is an unrounded value and the calculation control indicators provide information for generating an arithmetically correct rounded result from the intermediate result vector.

12 . The microprocessor of claim 1 , wherein the calculation control indicators provide an indication of which sign to assign to a zero result, if the final result is a zero value.

13 . A microprocessor comprising:
a plurality of instruction execution units configured to generate unrounded results and a plurality of rounding indicators for rounding the unrounded results; and a rounding cache external to the instruction execution units configured to store the plurality of rounding indicators.

14 . The microprocessor of claim 13 , wherein the rounding cache is an associative cache.

15 . The microprocessor of claim 13 , further comprising a general purpose memory store, distinct from the rounding cache, for storing unrounded results generated by the plurality of instruction execution units.

16 . The microprocessor of claim 13 , further comprising a rounding bit transfer path, a result bus distinct from the rounding bit transfer path, and a general purpose memory store, wherein the instruction execution units are configured to output the unrounded results to the result bus and to output the rounding indicators on the rounding bit transfer path to the rounding cache.

17 . The microprocessor of claim 13 , wherein at least one of the plurality of instruction execution units is configured to generate an unrounded result in response to an instruction of a first type and a rounded result in response to an instruction of a second type.

18 . The microprocessor of claim 13 , wherein the microprocessor is configured to supply (a) an unrounded result generated by a first one of the plurality of instruction execution units to a second one of the plurality of instruction execution units and (b) at least one of the plurality of rounding indicators from the rounding cache to the second one of the plurality of instruction execution units; and wherein the second one of the plurality of instruction execution units is configured to perform a mathematical operation on at least the unrounded result operand to generate a final rounded result using the supplied at least one of the plurality of rounding indicators.

19 . A microprocessor comprising:
a first instruction execution unit operable to generate an intermediate result vector and a plurality of calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed; and a forwarding bus external to the instruction execution unit configured to forward the intermediate result vector and the plurality of calculation control indicators to a second instruction execution unit.

20 . The microprocessor of claim 19 , wherein the first instruction execution unit is configured to generate an unrounded result in response to an instruction of a first type and a rounded result in response to an instruction of a second type.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Elmer Thomas

Classifications

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F7/485

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F7/49957

  Implementation of IEEE-754 Standard · CPC title