Lithography model calibration

Patent metadata

Field	Value
Publication number	US-11061318-B2
Application number	US-202016748551-A
Country	US
Kind code	B2
Filing date	Jan 21, 2020
Priority date	Feb 28, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

First claim

What is claimed is:

1. A method of semiconductor device fabrication, comprising:
simulating an ideal image using measured contour data and fitted conventional model terms including both an optical model portion and a resist model portion;
using the fitted conventional model terms and a mask layout to provide a conventional model aerial image;
generating a plurality of mask raster images using the mask layout, wherein the plurality of mask raster images is generated for each measurement site of the measured contour data; and
training a neural network to mimic the ideal image;
wherein the simulated ideal image provides a target output of the neural network, and wherein the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

2. The method of claim 1 , wherein the ideal image includes simulated contour data that is substantially equal to corresponding contour measurement data.

3. The method of claim 1 , wherein each of the plurality of mask raster images for a given measurement site have different pixel sizes.

4. The method of claim 1 , further comprising: in response to the training the neural network, generating a calibrated lithography model.

5. The method of claim 4 , wherein the calibrated lithography model is used to implement an optical proximity correction (OPC) process, an inverse lithography technology (ILT) process, or a mask process correction (MPC) process.

6. The method of claim 4 , further comprising:
using the calibrated lithography model to generate a modified mask layout pattern;
fabricating a mask based on the modified mask layout pattern; and
using the mask based on the modified mask layout pattern to pattern a wafer.

7. The method of claim 1 , wherein the training the neural network further includes generating a weighting matrix corresponding to the ideal image.

8. The method of claim 1 , wherein the training the neural network further includes using the neural network to simulate an image.

9. The method of claim 8 , wherein the training the neural network further includes calculating an objective function by comparing the image simulated by the neural network to the ideal image.

10. The method of claim 9 , further comprising: determining that a calculated value of the objective function satisfies a target level, and based on the determining, providing a final machine learning (ML)-assisted model image, wherein the ML-assisted model image is substantially equal to the ideal image.

11. The method of claim 9 , further comprising: determining that a calculated value of the objective function does not satisfy a target level, and based on the determining, adjusting one or more parameters of the neural network using a backpropagation method.

12. The method of claim 1 , wherein the ideal image includes simulated critical dimension (CD) data and simulated contour data that is substantially equal to corresponding CD measurement data and contour measurement data.

13. A method of semiconductor device fabrication, comprising:
providing a plurality of images to a neural network, wherein the plurality of images provides a target output of the neural network, and wherein the plurality of images includes a plurality of ideal images including simulated critical dimension (CD) data and simulated contour data that is substantially equal to corresponding CD measurement data and contour measurement data;
providing an aerial/resist image and a plurality of mask raster images as inputs to the neural network;
based on the target output and the inputs to the neural network, calculating an objective function by comparing a plurality of neural network generated images to the plurality of images; and
after the calculating the objective function, generating a calibrated lithography model.

14. The method of claim 13 , wherein each of the plurality of mask raster images for a given measurement site have different pixel resolutions.

15. The method of claim 13 , further comprising: generating weighting matrices for each image of the plurality of images.

16. The method of claim 13 , wherein the neural network crops the aerial/resist image and the plurality of mask raster images in a region corresponding to a pixel that is being processed by the neural network.

17. A method of semiconductor device fabrication, comprising:
training a neural network to output an ideal image, the training comprising:
providing the ideal image, an aerial/resist image, and a plurality of mask raster images to the neural network, wherein the ideal image is a target output of the neural network, wherein the aerial/resist image and the plurality of mask raster images are inputs to the neural network, and wherein the ideal image includes simulated critical dimension (CD) data and simulated contour data that is substantially equal to corresponding CD measurement data and contour measurement data;
based on the ideal image, the aerial/resist image, and the plurality of mask raster images, using the neural network to generate a simulated image;
calculating an objective function by comparing the simulated image to the ideal image; and
after the calculating the objective function, generating a final machine learning (ML)-assisted model image; and

in response to the training the neural network, generating a calibrated lithography model.

18. The method of claim 17 , further comprising:
using the calibrated lithography model to generate a modified mask layout pattern;
fabricating a mask based on the modified mask layout pattern; and
using the mask based on the modified mask layout pattern to pattern a wafer.

19. The method of claim 17 , wherein the aerial/resist image and each of the plurality of mask raster images are neurons within an input layer of the neural network.

20. The method of claim 17 , wherein the neural network includes more than one fully connected layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Shih-Hsiang
• Huang Hsu-Ting
• Liu Ru-Gun

Classifications

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• G06N3/045

  Combinations of networks · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• G03F7/70441

  Optical proximity correction [OPC] · CPC title

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title