Method and apparatus for integrated circuit mask patterning

Patent metadata

Field	Value
Publication number	US-9870443-B2
Application number	US-201514949713-A
Country	US
Kind code	B2
Filing date	Nov 23, 2015
Priority date	Aug 1, 2013
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

First claim

What is claimed is:

1. A method comprising:
receiving a design layout of an integrated circuit (IC), the design layout having a first main feature; and
adding a negative assist feature to the design layout, wherein:
the negative assist feature has a width,
the negative assist feature divides the first main feature into a second main feature and a third main feature by the width, and
the width is sub-resolution in a photolithography process;

performing an optical proximity correction (OPC) process to the second main feature and the third main feature to optimize the design layout; and
performing a mask rule checking (MRC) process to the optimized design layout.

2. The method of claim 1 , wherein the second and the third main features meet a plurality of mask creation rules.

3. The method of claim 1 , wherein the first main feature is in a shape of a concave polygon.

4. The method of claim 1 , wherein the photolithography process uses one of: an ultraviolet (UV) lithography process, an extreme ultraviolet (EUV) lithography process, an electron beam lithography process, an X-ray lithography process and an ion beam lithography process.

5. The method of claim 1 , further comprising:
forming a mask using the IC design layout with the negative assist feature; and
forming a pattern on a wafer using the mask and the photolithography process.

6. The method of claim 1 , further comprising:
performing a lithography process checking (LPC) to the second and third main features to generate a plurality of contours; and
adjusting the negative assist feature and repeating the performing the OPC process and the performing the MRC process if the plurality of contours do not meet a target boundary.

7. The method of claim 6 , wherein the target boundary is defined by an outer boundary of the first main feature.

8. The method of claim 6 , wherein the adjusting the negative assist feature includes one of:
changing location of the negative assist feature in the design layout while the negative assist feature still divides the first main feature;
increasing the width; and
decreasing the width.

9. The method of claim 1 , wherein performing the MRC process includes checking at least one dimension of the second main feature, at least one dimension of the third main feature, and at least one dimension of the negative assist feature.

10. A method, comprising:
receiving a circuit design layout having a printing feature;
identifying a negative optical proximity correction (OPC) feature corresponding to a portion of the printing feature to remove, wherein the negative OPC feature has a width that corresponds to a sub-resolution width;
determining that the negative OPC feature complies with a mask rule check;
based on determining that the negative OPC feature complies with the mask rule check, updating the circuit design layout to apply the negative OPC feature to the printing feature; and
after updating the circuit design layout to apply the negative OPC feature, determining that the applying of the negative OPC feature to the printing feature produces a resulting feature that complies with the mask rule check.

11. The method of claim 10 , wherein the applying of the negative OPC feature separates the printing feature into a first sub-feature and a second sub-feature, the method further comprising: determining that the first sub-feature and the second sub-feature comply with the mask rule check.

12. The method of claim 10 further comprising performing an OPC correction after the updating of the circuit design layout to apply the negative OPC feature and before the determining that the result of the applying of the negative OPC complies with the mask rule check.

13. The method of claim 12 , wherein the OPC correction results in a further modification to the printing feature.

14. The method of claim 10 further comprising fabricating a lithographic photomask based on the updated circuit design layout.

15. The method of claim 10 , further comprising:
performing a lithography process check on the updated circuit design layout; and
adjusting at least one of: a location or the width of the negative OPC feature based on the lithography process check.

16. A method comprising:
receiving a circuit layout for a photolithographic mask, wherein the circuit layout includes a feature;
identifying a portion of the feature to remove,
determining that the portion complies with a mask rule check;
removing the portion of the feature from the circuit layout based on determining that the portion complies with the mask rule check;
performing the mask rule check on a result of removing the portion of the feature;
performing a lithography process check on the result of removing the portion of the feature; and
adjusting at least one of: a location or a size of the removed portion based on the lithography process check.

17. The method of claim 16 , further comprising performing an optical proximity check process on the circuit layout after removing the portion of the feature.

18. The method of claim 17 , wherein the performing of the optical proximity check results in a further modification to the feature.

19. The method of claim 16 , wherein the portion has a width that is a sub-resolution width.

20. The method of claim 16 , wherein the removing of the portion of the feature from the circuit layout defines a first sub-feature and a second sub-feature, wherein the first sub-feature is separate from the second sub-feature, and wherein the first sub-feature includes a protruding portion extending towards the second sub-feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Chin-Min
• Chen Bo-Han
• Tsay Cherng-Shyan
• Lai Chien Wen
• Lin Hua-Tai
• Chang Chia-Cheng
• Yeh Lun-Wen
• Yang Shun-Shing

Classifications

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F17/5081 Primary

  Physics · mapped topic