Backplane footprint for high speed, high density electrical connectors

US11057995B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11057995-B2
Application numberUS-201916435781-A
CountryUS
Kind codeB2
Filing dateJun 10, 2019
Priority dateJun 11, 2018
Publication dateJul 6, 2021
Grant dateJul 6, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive element having a recess in a surface thereof. The recess is configured to receive a tip portion of the connector lead of the surface mount connector. The printed circuit board may have via patterns including signal vias and ground vias.

First claim

Opening claim text (preview).

What is claimed is: 1. A printed circuit board comprising: at least one dielectric layer; and at least one conductive element formed on the dielectric layer and configured for solder attachment to a connector lead of a surface mount connector, the conductive element having a recess in a surface thereof, wherein the recess is configured to be smaller in diameter than the connector lead and is configured to receive only a tip portion of the connector lead, wherein the conductive element is part of a via that extends through the dielectric layer, wherein the at least one dielectric layer comprises a plurality of layers including conductive layers separated by dielectric layers, and the via extends from an upper surface of the printed circuit board through one or more of the plurality of layers, and wherein the via is configured for attachment to a superelastic connector lead of the surface mount connector. 2. The printed circuit board as defined in claim 1 , wherein the recess has a depth in a range of 0.05 mm to 0.30 mm. 3. The printed circuit board as defined in claim 1 , wherein the recess includes at least one of a conical portion, a truncated conical portion, and a hemispherical portion. 4. The printed circuit board as defined in claim 1 , wherein the recess is configured to allow a tip portion of the connector lead of the surface mount connector to extend below the upper surface of the printed circuit board. 5. The printed circuit board as defined in claim 1 , wherein the via includes a conductive pad on the upper surface of the printed circuit board and wherein the conductive pad has a larger diameter than the conductive element of the via. 6. A printed circuit board comprising: a plurality of layers including conductive layers separated by dielectric layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: first and second signal vias extending from a first surface of the printed circuit board to a breakout layer of the conductive layers; and ground vias connected to one or more of the conductive layers, wherein the signal vias and the ground vias each include a conductive element having a recess in a surface thereof, wherein each conductive element is configured for solder attachment to a connector lead of a surface mount connector and wherein the recess is configured to be smaller in diameter than the connector lead and is configured to receive only a tip portion of the connector lead. 7. The printed circuit board as defined in claim 6 , wherein each recess has a depth in a range of 0.05 mm to 0.30 mm. 8. The printed circuit board as defined in claim 1 , wherein the conductive element has a wall thickness in a region of the recess in a range of 0.02 mm to 0.08 mm. 9. The printed circuit board as defined in claim 1 , wherein the recess has an aspect ratio of depth to width in a range of 1 to 4. 10. A printed circuit board comprising: a plurality of layers including conductive layers separated by dielectric layers; and at least one via pattern formed in the plurality of layers, the via pattern comprising: first and second signal conductors for attachment of respective first and second signal leads of a component to an upper surface of the printed circuit board and for connection of the first and second signal leads of the component to a breakout layer of the conductive layers; and at least one ground conductor for attachment to a ground lead of the component and for connection of the ground lead of the component to a ground plane of the conductive layers, wherein each of the first and second signal conductors and the at least one ground conductor has a recess in a surface thereof and wherein the recess is configured to be smaller in diameter than the connector lead and is configured to receive only a tip portion of the connector lead. 11. The printed circuit board as defined in claim 10 , wherein the first and second signal conductors are configured for connection to the first and second signal leads of the component at the upper surface of the printed circuit board. 12. The printed circuit board as defined in claim 10 , wherein the first and second signal conductors include signal vias that extend through the layers of the printed circuit board to the breakout layer. 13. The printed circuit board as defined in claim 10 , wherein the at least one ground conductor includes a ground via that extends through one or more layers of the printed circuit board to the ground plane. 14. The printed circuit board as defined in claim 10 , wherein the first and second signal conductors are configured for solder attachment to the first and second signal leads of the component.

Assignees

Inventors

Classifications

  • H05K1/115Primary

    Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • Edge mounted components, e.g. terminals · CPC title

  • Tapered, e.g. tapered hole, via or groove · CPC title

  • Coupling device provided on the PCB · CPC title

  • Concave hole or via · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11057995B2 cover?
A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive…
Who is the assignee on this patent?
Amphenol Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/115. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).