Evaluating a hole formed in an intermediate product

US11056404B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11056404-B1
Application numberUS-201916719856-A
CountryUS
Kind codeB1
Filing dateDec 18, 2019
Priority dateDec 18, 2019
Publication dateJul 6, 2021
Grant dateJul 6, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.

First claim

Opening claim text (preview).

What is claimed is: 1. An evaluation system, comprising: an imager configured to obtain an electron image of a hole that is formed by an etch process and exhibits a high aspect ratio and has a width of a nanometric scale, the hole exposing at least one layer of one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit; and a processing circuit configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. 2. The evaluation system according to claim 1 wherein the processing circuit is configured to evaluate whether the hole ended at the target layer by performing a classification of the hole to a class out of different classes that represent different possible outcomes of the etch process. 3. The evaluation system of according to claim 2 wherein the processing circuit is configured to perform the classification based on attributes related to at least a part of the electron image. 4. The evaluation system of according to claim 3 wherein the at least a part of the electron image has a radial symmetry. 5. The evaluation system of according to claim 3 wherein the attributes represent image signal properties related to etch process parameters. 6. The evaluation system of according to claim 2 wherein the classes comprise a properly etched hole, an under-etched hole, a first degree over-etched hole; and a second degree over-etched hole, wherein the second degree exceeds the first degree. 7. The evaluation system according to claim 1 wherein an over-etched hole of a first degree exposes a conductive layer of a single set of layers. 8. The evaluation system according to claim 1 wherein an over-etched hole of a second degree exposes conductive layers of sets of layers. 9. A method for evaluating a hole formed by an etch process and that exhibits a high aspect ratio and has a width of a nanometric scale, the method comprising: obtaining an electron image of the hole, the hole exposes at least one layer of one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit; and evaluating, by an evaluation system, and based on the electron image, whether the hole ended at a target layer of the intermediate product. 10. The method according to claim 9 wherein the evaluating comprises classifying the hole to a class out of different classes that represent different possible outcomes of the etch process. 11. The method according to claim 10 wherein the classifying is based on attributes related to at least a part of the electron image. 12. The method according to claim 11 wherein the at least a part of the electron image has a radial symmetry. 13. The method according to claim 12 wherein the attributes represent image signal properties related to etch process parameters. 14. The method according to claim 10 wherein the classes comprise a properly etched hole, an under-etched hole, a first degree over-etched hole; and a second degree over-etched hole, wherein the second degree exceeds the first degree. 15. The method according to claim 9 wherein an over-etched hole of a first degree exposes a conductive layer of a single set of layers. 16. The method according to claim 9 wherein an over-etched hole of a second degree exposes conductive layers of sets of layers. 17. A non-transitory computer readable medium that stores instructions for obtaining an electron image of a hole formed by an etch process and that exhibits a high aspect ratio and has a width of a nanometric scale, the hole exposing at least one layer of one or more sets of layers, wherein each set of layers comprises layers that differ from each other by their electron yield and belongs to an intermediate product manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit; and evaluating, by a computerized system and based on the electron image, whether the hole ended at a target layer of the intermediate product.

Assignees

Inventors

Classifications

  • H10P74/203Primary

    Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • comprising connection or disconnection of parts of a device in response to a measurement · CPC title

  • G11C5/02Primary

    Disposition of storage elements, e.g. in the form of a matrix array · CPC title

  • Semiconductor; IC; Wafer · CPC title

  • from scanning electron microscope · CPC title

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What does patent US11056404B1 cover?
An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit m…
Who is the assignee on this patent?
Applied Materials Israel Ltd
What technology area does this patent fall under?
Primary CPC classification H10P74/203. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).