Bonding surfaces for microelectronics

Patent metadata

Field	Value
Publication number	US-11056348-B2
Application number	US-201916371402-A
Country	US
Kind code	B2
Filing date	Apr 1, 2019
Priority date	Apr 5, 2018
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

First claim

The invention claimed is:

1. A method for preparing a surface for direct-bonding during a microelectronics fabrication process, comprising:
overfilling cavities and trenches in a dielectric surface with a temporary filler, wherein the dielectric surface comprises an oxide layer, wherein the oxide layer comprises a layer of silicon oxide and the temporary filler comprises silicon nitride, and wherein the oxide layer and the temporary filler are indistinguishable to a CMP process such that the CMP process has a 1:1 selectivity to the temporary filler as to the oxide layer with respect to both a chemical component of the CMP process and a mechanical component of the CMP process;
applying the CMP process to the temporary filler to planarize the temporary filler down to the dielectric surface; and
applying an etchant to the temporary filler to remove the temporary filler from the cavities and trenches, the etchant selective to the temporary filler and nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches.

2. The method of claim 1 , wherein the etchant comprises a phosphoric acid etchant to selectively remove the silicon nitride while being nonreactive with the silicon oxide.

3. The method of claim 1 , further comprising direct-bonding the dielectric surface to another dielectric surface.

4. The method of claim 1 , further comprising:
prior to the overfilling, preparing the dielectric surface for direct-bonding during a microelectronics fabrication process.

5. The method of claim 4 , further comprising direct-bonding the dielectric surface to another dielectric surface.

6. The method of claim 4 , wherein preparing the dielectric surface comprises planarizing the dielectric surface to a flatness comprising a depth of field of a photolithography system.

7. The method of claim 6 , further comprising direct-bonding the dielectric surface to another dielectric surface.

8. The method of claim 1 , further comprising:
prior to the overfilling, etching the cavities and trenches in the dielectric surface with a first etchant; and
stripping resist material from the dielectric surface.

9. A method, comprising:
preparing a dielectric surface of a wafer or die for direct-bonding during a microelectronics fabrication process, wherein the dielectric surface comprises an oxide layer;
masking the dielectric surface with a resist material for etching a cavity in the dielectric surface;
etching the cavity in the dielectric surface with a first etchant; stripping the resist material from the dielectric surface;
overflowing the cavity with a temporary filler to preserve edges of the cavity during a chemical-mechanical planarization (CMP) process, wherein the oxide layer comprises a layer of silicon oxide and the temporary filler comprises silicon nitride, and wherein the oxide layer and the temporary filler are indistinguishable to the CMP process such that the CMP process has a 1:1 selectivity to the temporary filler as to the oxide layer with respect to both a chemical component of the CMP process and a mechanical component of the CMP process;
applying the CMP process to planarize the temporary filler down to an interface between the temporary filler and the dielectric surface; and
removing the temporary filler from the cavity with a second etchant selective to the temporary filler and nonreactive to the dielectric surface and nonreactive to inner surfaces of the cavity.

10. The method of claim 9 , wherein the second etchant comprises a phosphoric acid to selectively etch the silicon nitride while remaining nonreactive to the silicon oxide.

11. The method of claim 9 , wherein the cavity has a depth penetrating through a layer of the silicon oxide into an underlying layer below the layer of silicon oxide.

12. The method of claim 9 , wherein preparing the dielectric surface before masking further comprises planarizing the dielectric surface to flatness comprising a depth of field of a photolithography system.

13. The method of claim 12 , further comprising direct-bonding the dielectric surface to another dielectric surface.

14. The method of claim 9 , further comprising direct-bonding the dielectric surface to another dielectric surface.

Assignees

• Invensas Bonding Tech Inc

Inventors

• Theil Jeremy Alfred

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W72/931

  Shapes of bond pads · CPC title