Offset compensation in ADC circuitry

Patent metadata

Field	Value
Publication number	US-11038522-B1
Application number	US-202016779976-A
Country	US
Kind code	B1
Filing date	Feb 3, 2020
Priority date	Feb 3, 2020
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

First claim

What is claimed is:

1. An apparatus comprising:
analog-to-digital conversion (ADC) circuitry, including a plurality of comparators susceptible to offset variation and including a shuffler circuit configured to shuffle input sources to the respective comparators; and
feedback circuitry configured and arranged with the ADC circuitry to:
detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators; and

compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

2. The apparatus of claim 1 , wherein the feedback circuitry is configured and arranged with the ADC circuitry to detect the offset variation in the output of each comparator by averaging the outputs of the plurality of comparators and determining the offset variation of each comparator as a difference between the output of the comparator and the averaged outputs.

3. The apparatus of claim 1 , wherein the feedback circuitry is configured and arranged with the ADC circuitry to compensate for residue offset common to the plurality of comparators by generating a feedback signal for each comparator based on the detected offset variation for that comparator and the residue offset.

4. The apparatus of claim 3 , wherein the feedback circuitry is configured to:
detect an amount of residue offset based on signal characteristics in a portion of the ADC circuitry that is different from the comparators; and
compensate for the detected residue offset in the comparators.

5. The apparatus of claim 3 , further including a feedback comparator coupled to receive an input signal provided to the plurality of comparators, and an integrator coupled to receive an output of the feedback comparator, wherein the feedback circuitry is configured to detect the residue offset in the apparatus using an output of the integrator.

6. The apparatus of claim 1 , further including dither circuitry configured to add a known dither signal to the ADC circuitry.

7. The apparatus of claim 1 , wherein the shuffler circuit is configured to randomly or pseudo-randomly shuffle the input sources to the respective comparators.

8. The apparatus of claim 1 , wherein the feedback circuitry is configured and arranged with the ADC circuitry to compensate for the offset variation by, for each comparator, generating a feedback signal based on the detected offset variation for the comparator and using the feedback signal to compensate for the offset variation in the comparator.

9. The apparatus of claim 1 , wherein the ADC circuitry and feedback circuitry are part of a multi-bit ADC quantizer.

10. The apparatus of claim 1 , wherein the feedback circuitry includes:
an adder circuit configured and arranged to add the outputs of the plurality of comparators;
a divider circuit configured and arranged to divide the added outputs by the number of comparators to provide an averaging value; and
for each comparator:
summing circuitry configured and arranged to detect the offset variation in the comparator based on an output of the comparator and the averaging value, and to provide an output based on the offset variation; and
integrator circuitry configured and arranged to integrate the output of the summing circuitry and provide the integrated output to the comparator as a feedback signal that adjusts the comparator to compensate for the offset variation.

11. A method comprising:
in analog-to-digital conversion (ADC) circuitry including a plurality of comparators susceptible to offset variation and a shuffler circuit, using the shuffler circuit to shuffle input sources to the respective comparators; and
in feedback circuitry,
detecting offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators; and

compensating for the offset variation in the comparators based on the offset differences between the respective comparators.

12. The method of claim 11 , wherein detecting the offset variation in the output of each comparator includes averaging the outputs of the plurality of comparators and determining the offset variation of each comparator as a difference between the output of the comparator and the averaged outputs.

13. The method of claim 11 , further including compensating for residue offset common to the plurality of comparators by generating a feedback signal for each comparator based on the detected offset variation for that comparator and the residue offset.

14. The method of claim 13 , further including:
detecting an amount of residue offset based on signal characteristics in a portion of the ADC circuitry that is different from the comparators; and
compensating for the detected residue offset in the comparators.

15. The method of claim 13 , further including detecting an amount of residue offset by detecting offset in a feedback comparator coupled to receive an input signal provided to the plurality of comparators.

16. The method of claim 11 , further including adding a known dither signal to the ADC circuitry.

17. The method of claim 11 , further including randomly or pseudo-randomly shuffling the input sources to the respective comparators.

18. The method of claim 12 , wherein compensating for the offset variation includes, for each comparator, generating a feedback signal based on the detected offset variation for the comparator and using the feedback signal to adjust the comparator.

19. A method comprising:
randomly shuffling quantizer reference levels of respective comparators in a quantizer of a delta sigma analog-to-digital converter (ADC), therein interchanging offsets of the respective comparators;
compensating for offset in each of the comparators by, for each comparator, providing an auxiliary offset input to the comparator based on an offset of the comparator and an average offset of the comparators.

20. The method of claim 19 , wherein compensating for the offset in each of the comparators includes removing offset differences between the comparators and removing noise generated via the random shuffling.

Assignees

• Nxp Bv

Inventors

• Witte Johan Frederik
• Breems Lucien Johannes
• Rutten Robert
• Bolatkale Muhammed
• Brekelmans Johannes Hubertus Antonius
• Bajoria Shagun
• Oude Essink Albertus Willibrordus

Classifications

• H03M1/0673

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/356 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494) · CPC title

• H03M3/328

  using dither · CPC title