Background estimation of comparator offset of an analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9602121-B2
Application number	US-201514793524-A
Country	US
Kind code	B2
Filing date	Jul 7, 2015
Priority date	Jul 7, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.

First claim

What is claimed is:

1. A method for estimating comparator offset of a sub-analog-to-digital converter (sub-ADC) of an analog to digital converter (ADC), the method comprising:
determining data samples of (1) a residue signal generated based on a difference between an input signal to the sub-ADC and a reconstructed version of the input signal or (2) an input signal to the sub-ADC, wherein data samples corresponds to two neighboring codes which are associated with a comparison made by a comparator of the sub-ADC;
tracking, over time, state information of the neighboring codes based on the data samples; and
determining an expected value, which estimates an offset of the comparator, based on the state information.

2. The method of claim 1 , further comprising:
calibrating or correcting for the offset based on the expected value.

3. The method of claim 1 , wherein the sub-ADC is a flash ADC or quantizer of any stage of a pipeline analog-to-digital converter.

4. The method of claim 1 , wherein:
the state information comprises (1) maximum values of the data samples corresponding to the first code and/or (2) minimum values of data samples corresponding to the neighboring code;
tracking the maximum values of the data samples comprises generating a new maximum value based on a current maximum value and a first difference between a current data sample of the data samples and the current maximum value; and
tracking the minimum values of the data samples comprises generating a new minimum value based on a current minimum value and a second difference between a current data sample of the data samples and the current minimum value.

5. The method of claim 4 , wherein:
the first difference is scaled by a first coefficient and is combined with the current maximum value; and
the second difference is scaled by a second coefficient and is combined with the current maximum value.

6. The method of claim 5 , wherein:
value of the first coefficient depends on whether the first difference is positive or negative; and
value of the second coefficient depends on whether the second difference is positive or negative.

7. The method of claim 1 , wherein:
the state information comprises (1) maximum values of the data samples corresponding to the first code and/or (2) minimum values of data samples corresponding to the neighboring code;
the data samples are based on the residual signal; and
determining the expected value comprises:
accumulating, over time, values representing a midpoint between a current maximum value and a current minimum value; and
determining the expected value based on the accumulated values.

8. The method of claim 1 , wherein:
the state information comprises (1) maximum values of the data samples corresponding to the first code and/or (2) minimum values of data samples corresponding to the neighboring code;
the data samples are based on the input to the sub-ADC; and
determining the expected value comprises:
accumulating, over time, the maximum values and/or the minimum values; and
determining the expected value based on the accumulated values.

9. The method of claim 1 , further comprising:
detecting one or more data samples cross a predetermined threshold; and
applying a correction to the comparator in response to detecting the one or more data samples crossing the predetermined threshold regardless of the expected value.

10. The method of claim 1 , further comprising:
calibrating or correcting for the comparator offset based on the expected value and a weighing factor controlling a time constant of the calibration or correction of the comparator offset.

11. The method of claim 1 , further comprising:
injecting a dither signal to the sub-ADC; and/or
shuffling comparators of the sub-ADC to ensure all comparators of the sub-ADC are used over time.

12. System for estimating comparator offset of a sub-analog-to-digital converter (sub-ADC) of an analog to digital converter (ADC), the system comprising:
first logic to observe data samples pertaining to a comparator of the sub-ADC, wherein the data samples include digital representations of (1) a residue signal generated based on a difference between an input signal to the sub-ADC and a reconstructed version of the input signal or (2) input to the sub-ADC, and the data samples corresponds to either a first code or a neighboring code;
peak detector to compute maximum values of the data samples corresponding to the first code;
trough detector to compute minimum values of data samples corresponding to the neighboring code; and
second logic to determine an expected value, which estimates an offset of the comparator, based on the maximum values and the minimum values.

13. The system of claim 12 , wherein:
the peak detector generates a new maximum value based on a current maximum value and a first difference between a current data sample of the data samples and the current maximum value; and
the trough detector generates a new minimum value based on a current minimum value and a second difference between a current data sample of the data samples and the current minimum value.

14. The system of claim 12 , wherein the digital representations of the residue signal comprises output codes from logic in a subsequent sub-ADC digitizing the residue.

15. The system of claim 12 , wherein digital representations of the input to the ADC comprises output codes from the sub-ADC.

16. The system of claim 12 , wherein:
the data samples are based on the residual signal; and
the second logic for determining the expected value based on the maximum values and minimum values comprises:
logic for accumulating, over time, values representing a midpoint between a current maximum value and a current minimum value; and
logic for determining the expected value based on the accumulated values.

17. The system of claim 12 , wherein:
the data samples are based on the input to the sub-ADC;
the second logic determining the expected value based on the maximum values and minimum values comprises:
logic for accumulating, over time, maximum values and minimum values; and
logic for determining the expected value based on the accumulated values.

18. The system of claim 12 , further comprising:
logic for detecting one or more of the data samples cross a predetermined threshold; and
logic for applying a correction to the comparator in response to detecting the one or more data samples crossing the predetermined threshold regardless of the expected value.

19. The system of claim 12 , further comprising:
logic for calibrating or correcting for the comparator offset based on the expected value and a weighing factor controlling a time constant of the calibration or correction of the comparator offset.

20. An apparatus for estimating comparator offset of a sub-analog-to-digital converter (sub-ADC) of an analog to digital converter (ADC), the apparatus comprising:
means for taking data samples associated with a comparator of the sub-ADC responsible for a first code and a neighboring code;
means for accumulating, over time, (1) maximum values of the data samples corresponding to a first code and (2) minimum values of data samples corresponding to a neighboring code; and
means for determining an estimated offset of the comparator based on the maximum values and minimum values after enough number of maximum and minimum value have been accumulated.

Assignees

• Analog Devices Inc

Inventors

• Ali Ahmed Mohamed Abdelatty
• Bhoraskar Paritosh
• Dinc Huseyin
• Morgan Andrew Stacy

Classifications

• H03M1/361 Primary

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/1028 Primary

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/1023

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/168

  and delivering the same number of bits · CPC title