Coulomb counter circuitry
US-12101097-B2 · Sep 24, 2024 · US
Limiting aging effects in analog differential circuits
US9531398B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9531398-B2 |
| Application number | US-201615042675-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 12, 2016 |
| Priority date | Mar 11, 2015 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
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Abstract
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Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for limiting aging effects on circuitry having an array of circuits, the method comprising: determining stress conditions associated with aging on the array of circuits; determining, based on the stress conditions, a first permutation of selected first ones of the circuits for a first time period and a second permutation of selected second ones of the circuits for a second time period, wherein said first and second permutations limit stress condit…
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Physics · mapped topic
Electricity · mapped topic
- H03M1/0609Primary
Electricity · mapped topic
- H03M1/06Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9531398B2 cover?
- Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutat…
- Who is the assignee on this patent?
- Analog Devices Inc, Analog Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification H03M1/0609. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).