Composite spacer enabling uniform doping in recessed fin devices

Patent metadata

Field	Value
Publication number	US-11038041-B2
Application number	US-201715792146-A
Country	US
Kind code	B2
Filing date	Oct 24, 2017
Priority date	Sep 2, 2015
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

First claim

What is claimed is:

1. A semiconductor device comprising:
an epitaxial semiconductor material present on at least one of a source region portion and a drain region portion of at least one fin structure, wherein the epitaxial semiconductor material includes:
a first portion having a conformal thickness on a vertical lower portion of a fin structure sidewall and; and
a second portion in contact with a horizontal upper surface of said at least one of the source portion and drain portion of the fin structure, the second portion being over and extending laterally beyond the first portion; and

a vertical spacer formed beneath the second portion and abutting the first portion, wherein the first portion is sandwiched between the vertical spacer and the fin structure sidewall, and wherein the epitaxial semiconductor material is doped with an n-type dopant and the n-type dopant is in the source and drain portions of the fin structure and is present in a uniform concentration along an entire height of the source and drain portions of the fin structure.

2. The semiconductor device of claim 1 , wherein the second portion of the epitaxial semiconductor material is wider than a combined width of two vertical spacer layers.

3. The semiconductor device of claim 1 , wherein the vertical spacer has a height that is at most equal to a height of the at least one fin structure.

4. The semiconductor device of claim 1 , wherein the vertical spacer has a tapered end.

5. The semiconductor device of claim 1 , wherein the uniform concentration of said n-type dopant along the entire height of the source and drain portions of the fin structure is present in a concentration ranging from 1×10 17 atoms/cm 3 to 1×10 21 atoms/cm 3 .

6. The semiconductor device of claim 1 , wherein the epitaxial semiconductor material is doped with a p-type dopant and the p-type dopant from the epitaxial semiconductor material is diffused into the source and drain portions of the fin structure, and is present in a uniform concentration along an entire height of the source and drain portions of the fin structure.

7. The semiconductor device of claim 6 , wherein the uniform concentration of said p-type dopant along the entire height of the source and drain portions of the fin structure is present in a concentration ranging from 1×10 17 atoms/cm 3 to 1×10 21 atoms/cm 3 .

8. The semiconductor device of claim 1 , wherein the first portion of the epitaxial semiconductor material is formed between the fin structure and two vertical spacers.

9. A semiconductor device comprising;
at least one fin structure;
a gate structure present on a channel portion of the at least one fin structure; and
an epitaxial semiconductor material present on at least one of a source region portion and a drain region portion of the at least one fin structure, wherein the epitaxial semiconductor material includes:
a first portion having a conformal thickness on a vertical lower portion of a fin structure sidewall and; and
a second portion in contact with a horizontal upper surface of said at least one of the source portion and drain portion of the fin structure, the second portion being over and extending laterally beyond the first portion; and

a dielectric vertical spacer formed beneath the second portion and abutting the first portion, wherein the first portion is sandwiched between the vertical spacer and the fin structure sidewall, and wherein the epitaxial semiconductor material is doped with an n-type dopant and the n-type dopant is in the source and drain portions of the fin structure and is present in a uniform concentration along an entire height of the source and drain portions of the fin structure.

10. The semiconductor device of claim 9 , wherein the second portion of the epitaxial semiconductor material is wider than the combined width of two vertical spacers.

11. The semiconductor device of claim 9 , wherein the epitaxial semiconductor material is merged epitaxial semiconductor material.

12. The semiconductor device of claim 9 , wherein the vertical spacer has a height that is at most equal to a height of the at least one fin structure.

13. The semiconductor device of claim 9 , wherein the uniform concentration of said n-type dopant along the entire height of the source and drain portions of the fin structure is present in a concentration ranging from 1×10 17 atoms/cm 3 to 1×10 21 atoms/cm 3 .

14. The semiconductor device of claim 9 , wherein the vertical spacer has a tapered end.

15. The semiconductor device of claim 9 , wherein the epitaxial semiconductor material is doped with a p-type dopant and the p-type dopant from the epitaxial semiconductor material is diffused into the source and drain portions of the fin structure, and is present in a uniform concentration along an entire height of the source and drain portions of the fin structure.

16. The semiconductor device of claim 15 , wherein the uniform concentration of said p-type dopant along the entire height of the source and drain portions of the fin structure is present in a concentration ranging from 1×10 17 atoms/cm 3 to 1×10 21 atoms/cm 3 .

17. A semiconductor device comprising;
at least one fin structure;
a gate structure present on a channel portion of the at least one fin structure; and
an epitaxial semiconductor material present on at least one of a source region portion and a drain region portion of the at least one fin structure, wherein the epitaxial semiconductor material includes
a first portion comprising two protrusions sandwiching the fin structure, each protrusion having a conformal thickness on a lower portion of the fin structure sidewall, and
a second portion present on an upper surface of said at least one of the source portion and drain portion of the fin structure, wherein the epitaxial semiconductor material is non-merged with adjacent epitaxial semiconductor material, the second portion being over and extending laterally beyond the first portion; and

a dielectric vertical spacer formed beneath the second portion and abutting the first portion, wherein the first portion is sandwiched between the vertical spacer and the fin structure sidewall, wherein the epitaxial semiconductor material is doped with an n-type dopant or a p-type dopant which is diffused into the source and drain portions of the fin structure, and is present in a uniform concentration along an entire height of the source and drain portions of the fin structure.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Liu Zuoguang
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title