Metallized junction FinFET structures

Patent metadata

Field	Value
Publication number	US-9627410-B2
Application number	US-201514718500-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

First claim

What is claimed is:

1. A FinFET structure comprising:
a semiconductor-on-insulator substrate including a bottom semiconductor layer and an electrically insulating layer adjoining the bottom semiconductor layer;
a plurality of semiconductor fins mounted to the substrate, each of the fins having base portions adjoining the electrically insulating layer and sidewalls including (110) surfaces;
a plurality of parallel gate structures operatively associated with the semiconductor fins, the gate structures including sidewalls and extending perpendicularly with respect to the semiconductor fins;
a first set of dielectric sidewall spacers adjoining the sidewalls of the gate structures;
a second set of dielectric sidewall spacers adjoining the first set of dielectric sidewall spacers and covering portions of the source/drain structures;
a plurality of pairs of unmerged epitaxial source/drain structures including (111) planes, each pair of source/drain structures being operatively associated with one of the semiconductor fins;
a plurality of parallel, fin-shaped cavities between and separating each pair of source/drain structures, the cavities extending to the electrically insulating layer of the semiconductor-on-insulator substrate, and
a metal silicide layer formed on the (111) planes of the epitaxial source/drain structures and adjoining the source/drain structures and filling the plurality of cavities.

2. The FinFET structure of claim 1 , further including an inter-level dielectric layer on the substrate and an opening in the inter-level dielectric layer exposing the metal silicide layer on the source/drain structures.

3. The FinFET structure of claim 2 , further including an electrically conductive contact bar in direct contact with the metal silicide layer.

4. The FinFET structure of claim 3 , further including doped extension junctions within the semiconductor fins.

5. The FinFET structure of claim 3 , wherein the source/drain structures consist essentially of doped silicon germanium.

6. The FinFET structure of claim 3 , wherein the source/drain structures consist essentially of doped silicon.

Assignees

• IBM

Inventors

• Doris Bruce B
• Kerber Pranita
• Reznicek Alexander
• Rubin Joshua M

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title