Semiconductor device and manufacturing method

Patent metadata

Field	Value
Publication number	US-11038028-B2
Application number	US-201916406773-A
Country	US
Kind code	B2
Filing date	May 8, 2019
Priority date	May 9, 2018
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the semiconductor substrate comprises a first dopant and a second dopant, and a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant, and wherein a vertical extension of the first dopant into the semiconductor substrate from the first main surface ends at a bottom of a first semiconductor substrate portion at a first vertical distance to the first main surface;
forming a semiconductor layer on the first main surface;
forming semiconductor device elements in the semiconductor layer; and
reducing a thickness of the semiconductor substrate by removing a material of the semiconductor substrate from the second main surface at least up to the first semiconductor substrate portion,
wherein the first dopant is introduced through the first main surface into the semiconductor substrate by a plasma based ion implantation process at a dose in a range from 10 16 cm −2 to 10 18 cm −2 .

2. The method of claim 1 , wherein providing the semiconductor substrate comprises:
introducing the second dopant through the first main surface into the semiconductor substrate by at least one of a diffusion process, an ion implantation process and a plasma based ion implantation process.

3. The method of claim 1 , further comprising:
forming a diffusion barrier on the first main surface of the semiconductor substrate after introduction of the first dopant; and
subsequently performing a thermal diffusion process to broaden a vertical concentration profile of the first dopant.

4. The method of claim 1 , wherein the first dopant and the second dopant are introduced through the first main surface into the semiconductor substrate one after the other at different doses and/or energies.

5. The method of claim 4 , wherein a vertical concentration profile of the first dopant and a vertical concentration profile of the second dopant are superimposed by coordinating i) a dose, an energy and a thermal budget for broadening a vertical concentration profile of the first dopant, and ii) a dose, an energy and a thermal budget for broadening a vertical concentration profile of the second dopant.

6. The method of claim 5 , wherein the dose, the energy and the thermal budget for broadening a vertical concentration profile N 1 ( y ) of the first dopant and the dose, the energy and the thermal budget for broadening a vertical concentration profile N 2 ( y ) of the second dopant are coordinated to satisfy:

∫
0
t

⁢



N
⁢

⁢
1
⁢

(
y
)

-

N
⁢

⁢
2
⁢

(
y
)



⁢
dy

∫
0
t

⁢

N
⁢

⁢
1
⁢

(
y
)

⁢
dy

<

100
⁢
%

,

where t is a thickness of the semiconductor substrate after reducing the thickness of the semiconductor substrate.

7. The method of claim 1 , wherein, after reducing the thickness of the semiconductor substrate, a vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

8. The method of claim 1 , wherein an average concentration of a vertical concentration profile of the first dopant between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface is in a range from 5×10 18 cm −3 to 5×10 20 cm −3 .

9. The method of claim 1 , wherein the second dopant constitutes a background doping of the semiconductor substrate in a range from 10 18 cm −3 to 10 21 cm −3 .

10. The method of claim 1 , wherein the first dopant is one element selected from the group consisting of arsenic, phosphorus, and antimony, and wherein the second dopant is a different element selected from the group consisting of arsenic, phosphorus and antimony.

11. The method of claim 1 , wherein the first dopant is one element selected from the group consisting of boron, aluminum, and gallium, and the wherein second dopant is a different element selected from the group consisting of boron, aluminum, and gallium.

12. The method of claim 1 , wherein providing the semiconductor substrate comprises:
after introducing the first dopant but before reducing the thickness of the semiconductor substrate, forming a sealing layer on the second main surface of the semiconductor substrate.

13. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the semiconductor substrate comprises a first dopant and a second dopant, and a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant, and wherein a vertical extension of the first dopant into the semiconductor substrate from the first main surface

Assignees

• Infineon Technologies Ag

Inventors

• Muri Ingo
• Baumgartl Johannes Konrad
• Hellmund Oliver
• Ludwig Jacob Tillmann
• Moder Iris
• Neidhart Thomas Christian
• Schmidt Gerhard
• Schulze Hans-Joachim

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/1204 Primary

  from a plasma phase · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title