FinFET and method for forming the same

Patent metadata

Field	Value
Publication number	US-9893182-B2
Application number	US-201614989215-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jan 6, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

The present disclosure provides a method for forming a field-effect fin transistor (FinFET) structure. The method includes providing a substrate with fin structures; forming a gate structures across the fin structures; and forming ion implantation regions in the fin structures at both sides of the gate structure. The method also includes removing top portions of the fin structures at both sides of the gate structure to form remaining portions of the fin structures; forming a first semiconductor material layer on the remaining portions of the fin structures; and forming a second semiconductor material layer on the first semiconductor material layer, the second semiconductor material being doped with barrier-lowering ions. The method further includes forming a metal layer on the second semiconductor material layer, and performing an annealing process on the metal layer to form a contact-resistance-reducing layer.

First claim

What is claimed is:

1. A method for forming a field-effect fin transistor (FinFET) structure, comprising:
providing a substrate with fin structures;
forming a gate structures across the fin structures;
forming a first spacer material layer on top surfaces and sidewalls of the fin structures;
forming ion implantation regions in the fin structures at both sides of the gate structure;
forming a second spacer material layer on the first spacer material layer;
performing a recess etching process on the first spacer material layer and the second spacer material layer to form the fin spacers;
removing top portions of the fin spacers;
removing top portions of the fin structures at both sides of the gate structure to form remaining portions of the fin structures, wherein a bottommost surface of the remaining portion of a fin structure is above a topmost surface of a corresponding fin spacer with the top portion of the fin spacer removed;
forming a first semiconductor material layer on the remaining portions of the fin structures, the first semiconductor material layer being doped with ions for forming a source and a drain of the FinFET structure;
forming a second semiconductor material layer on the first semiconductor material layer, the second semiconductor material being doped with barrier-lowering ions;
forming a metal layer on the second semiconductor material layer, and
performing an annealing process on the metal layer to form a contact-resistance-reducing layer.

2. The method according to claim 1 , wherein the height of the removed top portion of the fin structure is greater than or equal to about ⅙ of a total height of the fin structure and is less than or equal to about ⅓ of the total height of the fin structure.

3. The method according to claim 1 , wherein the ion implantation regions include at least one of a lightly-doped drain (LDD) ion implantation region and a Halo ion implantation region.

4. The method according to claim 1 , wherein the barrier-lowering ions include one or more types of sulfur ions, selenium ions, arsenic ions, antimony ions, and germanium ions.

5. The method according to claim 1 , wherein the first semiconductor material layer is made of silicon, silicon carbide, or a combination of silicon and silicon carbide; and the second semiconductor material layer is made of silicon.

6. The method according to claim 5 , wherein the contact-resistance-reducing layer is made of metal silicide.

7. The method according to claim 1 , wherein the metal layer is made of one or more of cobalt, molybdenum, platinum, tantalum, titanium, and tungsten.

8. The method according to claim 1 , wherein one or more of in-situ doping growth and epitaxial deposition are used to form the first semiconductor material layer and the second semiconductor material layer.

9. A method for forming a field-effect fin transistor (FinFET) structure, comprising:
providing a substrate with fin structures;
forming a gate structures across the fin structures;
forming ion implantation regions in the fin structures at both sides of the gate structure;
removing top portions of the fin structures at both sides of the gate structure to form remaining portions of the fin structures;
forming a first semiconductor material layer on the remaining portions of the fin structures, the first semiconductor material layer being doped with ions for forming a source and a drain of the FinFET structure;
forming a second semiconductor material layer on the first semiconductor material layer, the second semiconductor material being doped with barrier-lowering ions, doping phosphorus ions into the second semiconductor material layer when forming the second semiconductor material layer, a concentration of the phosphorus ions being higher than a concentration of the barrier-lowering ions;
forming a metal layer on the second semiconductor material layer, and
performing an annealing process on the metal layer to form a contact-resistance-reducing layer.

10. The method according to claim 9 , wherein a height of a removed top portion of a fin structure is greater than or equal to about ⅙ of a total height of the fin structure and is less than or equal to about ⅓ of the total height of the fin structure.

11. The method according to claim 9 , wherein the ion implantation regions include at least one of a lightly-doped drain (LDD) ion implantation region and a Halo ion implantation region.

12. The method according to claim 9 , wherein the barrier-lowering ions include one or more types of sulfur ions, selenium ions, arsenic ions, antimony ions, and germanium ions.

13. An N-type field effect fin transistor (FinFET) structure, comprising:
a substrate with fin structures;
a gate structure positioned across the fin structures;
fin spacers surrounding the fin structures;
ion implantation regions in the fin structures on both sides of the gate structure;
a source and a drain formed on the fin structures; and
a contact-resistance-reducing layer formed on the source and the drain of the FinFET structure, wherein:
top portions of the fin spacers are removed;
top portions of the fin structures on both sides of the gate structure are removed to form remaining portions of the fin structures;
a bottommost surface of the remaining portion of the fin structure is above a topmost surface of a corresponding fin spacer with the top portion of the fin spacer removed;
a first semiconductor material layer is formed on the remaining portions of the fin structures, the first semiconductor material layer being doped with ions for forming a source and a drain of the FinFET; and
the contact-resistance-reducing layer is formed on the first semiconductor material layer.

14. The FinFET structure according to claim 13 , wherein the height of the removed top portion of the fin structure is greater than or equal to about ⅙ of a total height of the fin structure and is less than or equal to about ⅓ of the total height of the fin structure.

15. The FinFET structure according to claim 13 , wherein the contact-resistance-reducing layer includes a dipole layer at a bottom boundary of the contact-resistance-reducing layer.

16. The FinFET structure according to claim 15 , wherein the dipole layer is formed by one or more types of sulfur ions, selenium ions, arsenic ions, antimony ions, and germanium ions.

17. The FinFET structure according to claim 13 , wherein the ion implantation regions includes at least one of a lightly-doped drain (LDD) ion implantation region and a Halo ion implantation region.

18. The FinFET structure according to claim 13 , wherein the contact-resistance-reducing layer is made of metal silicide.

19. The FinFET structure according to claim 18 , wherein the metal silicide is formed by silicon and one or more of cobalt, molybdenum, platinum, tantalum, titanium, and tungsten.

20. The FinFET structure according to claim 13 , wherein the first semiconductor material layer is made of silicon, silicon carbide, or a combination or silicon and silicon carbide.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Li Yong

Classifications

• H10P14/6928

  the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides · CPC title

• H01L29/7833 Primary

  Electricity · mapped topic

• H01L21/02142

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic