Semiconductor device

Patent metadata

Field	Value
Publication number	US-11037988-B2
Application number	US-202016802976-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Jul 6, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a lower electrode and a molding film surrounding the lower electrode, the molding film including SiN;
forming a first memory cell extending in a first direction and including a phase change memory,
an ovonic threshold switch (OTS) and an upper electrode, the phase change memory and the OTS being disposed between the lower electrode and the upper electrode;
forming a first capping film at a first temperature, the first capping film extending along sidewalls of the phase change memory, sidewalls of the OTS, sidewalls of the upper electrode, and an upper surface of the upper electrode;
forming a second capping film directly on the first capping film at a second temperature higher than the first temperature; and
removing a portion of the second capping film and a portion of the first capping film to expose the upper surface of the upper electrode,
wherein each of the first and second capping films includes a nitride-based insulating material;
wherein the first capping film is formed through a first plasma process using a N2 gas without a NH3 gas and
the second capping film is formed through a second plasma process using a NH3 gas, and the second plasma process includes:
performing a first sub plasma process using a N2 gas; and
performing a second sub plasma process using the NH3 gas after the first sub plasma process.

2. The method of claim 1 , wherein forming the second capping film proceeds in-situ in succession to forming the first capping film.

3. The method of claim 1 , wherein:
forming the first capping film includes a dose operation, a first purge operation, a radio frequency (RF) plasma operation, and a second purge operation which are performed successively, and
the RF plasma operation uses the first N2 plasma.

4. The method of claim 1 , wherein:
forming o the second capping film includes a dose operation, a first purge operation, a radio frequency (RF) plasma operation, a NH 3 processing operation, and a second purge operation which are performed successively,
the RF plasma operation uses the second N2 plasma, and the NH 3 processing operation uses the NH 3 plasma.

5. The method of claim 1 , further comprising:
forming a second memory cell extending in the first direction and including a second phase change memory and a second OTS while the first memory cell is formed,
wherein the second memory cell is spaced apart from the first memory cell in a second direction intersecting the first direction,
wherein the first capping film is continuous in the first direction along the sidewalls of the first memory cell and sidewalls of the second memory cell, and in the second direction between the sidewalls of the first and second memory cells, and
wherein the second capping film entirely fills a space between the first and second memory cells.

6. The method of claim 1 , wherein each of the first and second capping films includes at least one of SiN, SiON, SiCN, and SiBN.

7. The method of claim 1 , wherein the first capping film extends continuously between an upper surface of the mold film and a bottom surface of the second capping film.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Uk
• Park Jeong Hee
• Park Seong Geon
• Park Soon Oh
• Lee Jung Moo

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C13/003

  Cell access · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title