Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9515250-B2
Application number	US-201414586748-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Feb 28, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An electronic device comprising a semiconductor memory unit includes: variable resistance patterns formed over a substrate; a protective layer formed over the substrate including the variable resistance patterns and including a leakage current blocking layer that is spaced apart from the variable resistance patterns; and contact plugs formed adjacent to the variable resistance patterns over the substrate and penetrating through the protective layer to be coupled with the substrate.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory unit that includes:
a first interlayer dielectric layer which is formed over a substrate;
a variable resistance pattern formed over the first interlayer dielectric layer;
a protective layer formed over the substrate to cover the variable resistance pattern and the first interlayer dielectric layer; and
a contact plug formed adjacent to the variable resistance pattern over the substrate and configured to be located outside the protective layer to penetrate through the first interlayer dielectric layer to be coupled with the substrate,
wherein the protective layer includes (1) a first protective layer that has a uniform thickness and is in contact with the variable resistance pattern and the first interlayer dielectric layer and (2) a second protective layer that is in contact with the first protective layer to cover the first protective layer, has a spatially varying thickness in different parts of the second protection layer to include an overhang portion in contact with an upper portion of a sidewall of and a top portion above the variable resistance pattern to protect the variable resistance pattern from oxidation.

2. The electronic device according to claim 1 , further comprising a leakage current blocking layer that is spaced apart from the variable resistance pattern to cover the first interlayer dielectric layer and to contact a sidewall of the protective layer, wherein the leakage current blocking layer is disposed at a position such that the contact plug penetrates through the leakage current blocking layer and the first interlayer dielectric layer to be coupled to the substrate, and
the leakage current blocking layer surrounds the contact plug.

3. The electronic device according to claim 2 , wherein the protective layer and the leakage current blocking layer are formed of different materials.

4. The electronic device according to claim 2 , wherein the leakage current blocking layer includes an oxide.

5. The electronic device according to claim 2 , wherein the protective layer includes a nitride, and the leakage current blocking layer includes an oxynitride.

6. The electronic device according to claim 1 , wherein the variable resistance pattern includes a magnetic tunneling junction including a tunnel barrier interposed between two magnetic layers.

7. The electronic device according to claim 1 , further including:
a selection element formed in the substrate, and the contact plug is electrically connected to the selection element.

8. The electronic device according to claim 1 , further including another contact plug located above the variable resistance pattern and penetrating through the protective layer to be electrically connected to the variable resistance pattern.

9. The electronic device according to claim 1 , further comprising a leakage current blocking layer that is in contact with the protective layer and is formed of a material that is different from a material of the protective layer, wherein the leakage current blocking layer includes a portion formed over the variable resistance pattern and the portion is disposed on a surface of the protective layer or inside the protective layer.

10. The electronic device according to claim 1 , further comprising a leakage current blocking layer that is spaced apart from the variable resistance pattern to cover the first interlayer dielectric layer and to contact a sidewall of the protective layer, wherein the leakage current blocking layer includes a material, which is different from a material of the protective layer.

11. The electronic device according to claim 1 , wherein the first protective layer and the second protective layer include the same material.

12. The electronic device according to claim 11 , wherein the second protective layer has a denser film quality than the first protective layer.

13. An electronic device comprising a semiconductor memory unit that includes:
a substrate;
a first interlayer dielectric layer over the substrate;
a plurality of variable resistance patterns formed over the first interlayer dielectric layer, wherein each variable resistance pattern exhibits different resistance values to store data;
a protective layer formed over the first interlayer dielectric layer and variable resistance patterns, wherein the protective layer includes a first material; and
a leakage current blocking layer formed over portions of the substrate to cover spaces between the variable resistance patterns over the first interlayer dielectric layer and to be in contact with the protective layer, wherein the leakage current blocking layer includes a second material having better leakage characteristics than the first material,
wherein the protective layer includes (1) a first protective layer that has a uniform thickness and is in contact with the variable resistance patterns and the first interlayer dielectric layer and (2) a second protective layer that is in contact with the first protective layer to cover the first protective layer, and has a spatially varying thickness in different parts of the second protection layer to include an overhang portion in contact with an upper portion of a sidewall of and a top portion above each variable resistance pattern to protect the variable resistance pattern from oxidation.

14. The electronic device of claim 13 , wherein the protective layer and the leakage current blocking layer are interleaved over the first interlayer dielectric layer to form portions of the protective layer that are discontinuous from portions of the leakage current blocking layer.

15. The electronic device of claim 13 , wherein
the first material includes a nitride and the second material includes an oxide.

16. The electronic device of claim 13 , wherein the second protective layer has a superior film quality to the first protective layer.

17. The electronic device of claim 13 , wherein
the leakage current blocking layer is free of a contact with the variable resistance patterns.

18. An electronic device comprising a semiconductor memory unit that includes:
a substrate;
an interlayer dielectric layer over the substrate;
a plurality of variable resistance patterns formed over the interlayer dielectric layer, wherein each variable resistance pattern exhibits different resistance values to store data;
a protective layer formed over the interlayer dielectric layer and patterned to include different protective layer regions that cover the variable resistance patterns, wherein the protective layer includes (1) a first protective layer that has a spatially uniform thickness and is in contact with the variable resistance patterns and (2) a second protective layer that is in contact with the first protective layer to cover the first protective layer, and has a spatially varying thickness in different parts of the second protection layer to include an overhang portion in contact with an upper portion of a sidewall of and a top portion above each variable resistance pattern to protect the variable resistance pattern from oxidation;
a leakage current blocking layer formed over the interlayer dielectric layer and patterned to include different leakage current blocking layer portions located in spaces between the variable resistance patterns, wherein the leakage current blocking layer and the protective layer have different material compositions to prevent current leakage originating from the protective layer;
buried gates formed in the substrate; and
contact plugs located between the variable re

Assignees

• Sk Hynix Inc

Inventors

• Ha Ga-Young

Classifications

• H01L27/228

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10B53/00 Primary

  Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors · CPC title

• H10N50/80 Primary

  Constructional details · CPC title