Cross-point memory and methods for fabrication of same

Patent metadata

Field	Value
Publication number	US-2016133671-A1
Application number	US-201414535731-A
Country	US
Kind code	A1
Filing date	Nov 7, 2014
Priority date	Nov 7, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.

First claim

What is claimed is:

1 . A memory device, comprising
a plurality of variable resistance memory cell pillars, —wherein adjacent memory cell pillars are separated by a partially filled gap that includes a buried void, and —wherein the adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.

2 . The memory device of claim 1 , wherein the storage material comprises a phase change material.

3 . The memory device of claim 1 , wherein a seal region is formed in the gap above the buried void and filled with a gap-seal dielectric.

4 . The memory device of claim 3 , wherein the gap-seal dielectric covers at least portions of opposing sidewalls of the adjacent memory cell pillars below the seal region.

5 . The memory device of claim 4 , wherein a thickness of the gap-seal dielectric covering the opposing sidewalls below the seal region continuously decreases away from the seal region.

6 . The memory device of claim 4 , wherein the gap-seal dielectric does not cover at least portions of the opposing sidewalls of the adjacent memory cell pillars below the seal region.

7 . The memory device of claim 3 , wherein the gap-seal dielectric comprises silicon nitride.

8 . The memory device of claim 3 , wherein the gap further includes an isolation region above the seal region, the isolation region filled with a gap-fill dielectric different from the gap-seal dielectric.

9 . The memory device of claim 1 , wherein opposing sidewalls of the adjacent memory cell pillars are lined with liner dielectric materials in contact with the opposing sidewalls.

10 . The memory device of claim 1 , wherein each of the variable resistance memory cell pillars is surrounded by the buried void.

11 . A memory device, comprising:
a plurality of memory cell stacks, wherein each memory cell stack comprises a storage element comprising a phase change material, wherein adjacent memory cell stacks are separated by a gap which includes an enclosed void.

12 . The memory device of claim 11 , wherein each memory cell stack comprises upper and lower active elements, wherein one of the upper and lower active elements comprises the storage element and the other of the upper and lower active elements comprises a selector element.

13 . The memory device of claim 12 , wherein the upper active element comprises the storage element, and the upper active elements of the adjacent memory cell stacks are at least partially interposed by the enclosed void.

14 . The memory device of claim 13 , wherein the lower active elements of the adjacent memory cell stacks are at least partially interposed by the enclosed void.

15 . The memory device of claim 12 , wherein each memory cell stack further comprises an upper electrode formed on the upper active element, wherein the enclosed void does not extend above a top surface of the upper electrode.

16 . The memory device of claim 12 , wherein each memory cell stack is formed between an upper conductive line and a crossing lower conductive line, and wherein each memory cell stack further comprises an upper electrode formed on the upper active element, wherein the enclosed void does not extend above a top surface of the upper conductive line.

17 . The memory device of claim 11 , wherein each of the memory cell stacks is surrounded by the enclosed void.

18 . A memory device, comprising:
an array of memory pillars arranged in a plurality of rows of pillars aligned in a first lateral direction and a plurality of columns of pillars aligned in a second lateral direction crossing the first lateral direction, —wherein each memory pillar comprises a storage element comprising a phase change material, and —wherein at least two adjacent memory pillars are separated by a first gap having a first buried void.

19 . The memory device of claim 18 , wherein adjacent rows of pillars and adjacent columns of pillars are separated by continuous buried voids extending in the respective first and second lateral directions of the rows of pillars and columns of pillars.

20 . The memory device of claim 19 , wherein the continuous buried voids extending in the first lateral direction and the continuous buried voids extending in the second lateral direction intersect each other such that each memory pillar is surrounded by a continuous buried void.

21 . The memory device of claim 20 , wherein the continuous buried void surrounds the storage element.

22 . A method of forming a memory device, comprising:
forming a plurality of variable resistance memory cell pillars, wherein each memory cell pillar includes a storage element; and forming a buried void that interposes storage material elements of at least two adjacent ones of the memory cell pillars.

23 . The method of claim 22 , wherein forming the memory cell pillars includes:
forming a plurality of memory cell line stacks extending in a first direction, wherein each memory cell line stack includes a storage material line; and separating the memory cell line stacks in the first direction to form the memory cell pillars.

24 . The method of claim 23 , wherein forming the buried void comprises:
after forming the memory cell line stacks, partially filling a gap between adjacent memory cell line stacks with a gap-seal dielectric to form the buried void that forms a continuous buried void extending in the first direction.

25 . The method of claim 23 , wherein forming the buried void comprises:
after separating the memory cell line stacks to form the memory cell pillars, partially filling a gap between adjacent memory cell pillars with a gap-seal dielectric to form the buried void that forms a continuous buried void extending in a second direction.

26 . The method of claim 22 , wherein forming the memory cell pillars includes forming the storage element to include a phase change material.

27 . The method of claim 22 , wherein forming the buried void includes partially filling a gap between adjacent memory cell pillars with a gap-seal dielectric, wherein a seal region is formed in the gap above the buried void and filled with the gap-seal dielectric.

28 . The method of claim 27 , wherein partially filling includes covering at least portions of opposing sidewalls of the at least two adjacent ones of the memory cell pillars below the seal region with the gap-seal dielectric.

29 . The method of claim 28 , wherein partially filling includes not covering at least portions of opposing sidewalls of the at least two adjacent ones of the memory cell pillars below the seal region with the gap-seal dielectric.

30 . The method of claim 27 , wherein partially filling the gap comprises partially filling with silicon nitride.

31 . The method of claim 27 , further comprising forming an isolation region above the seal region and filling the isolation region with a gap-fill dielectric different from the gap-seal dielectric.

32 . The method of claim 22 , further comprising lining opposing sidewalls of the adjacent memory cell pillars with liner dielectric materials prior to forming the buried void.

33 . The method of claim 22 , wherein forming the buried void includes surrounding each of the variable resistance memory cell pillars.

Assignees

• Micron Technology Inc

Inventors

• Fantini Paolo
• Casellato Cristina
• Pellizzer Fabio

Classifications

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title