Analog-to-digital converter, sensor arrangement and method for analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-11031949-B2
Application number	US-201816492711-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 23, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

An analog-to-digital converter comprises a first integrator (40), a first converter input (19), a first reference voltage input (34), a capacitor array (68) comprising capacitor elements (171), and a rotation frequency control unit (37) providing a rotation signal (SRO) with at least two different values of a rotation frequency (fR). A first subset of capacitor elements (171) of the capacitor array (68) is coupled to the first converter input (19) and to an input side of the first integrator (40) in a first phase and is coupled to the first reference voltage input (34) and to the input side of the first integrator (40) in a second phase as a function of the rotation signal (SRO).

First claim

The invention claimed is:

1. An analog-to-digital converter,
wherein the analog-to-digital converter is implemented as a sigma-delta analog-to-digital converter and comprises
a first integrator,
a first converter input at which a first converter voltage is tapped,
a first reference voltage input,
a capacitor array comprising capacitor elements, and
a rotation frequency control unit providing a rotation signal with at least two different values of a rotation frequency,
wherein a capacitor element changes its location at the rotation frequency, and
wherein a first subset of capacitor elements of the capacitor array is coupled to the first converter input and to an input side of the first integrator in a first phase and is coupled to the first reference voltage input and to the input side of the first integrator in a second phase as a function of the rotation signal.

2. The analog-to-digital converter according to claim 1 , wherein a value of the rotation frequency of the rotation signal depends on a gain signal.

3. The analog-to-digital converter according to claim 2 , wherein a gain of the first integrator is set by the gain signal.

4. The analog-to-digital converter according to claim 3 , wherein the first integrator comprises a first amplifier and a first integrating capacitor having a number of further capacitor elements and
wherein a subset of the further capacitor elements of the first integrating capacitor is coupled to an input side of the first amplifier and to an output side of the first amplifier and the number of further capacitor elements in the subset is a function of the gain signal.

5. The analog-to-digital converter according to claim 1 ,
wherein the analog-to-digital converter comprises a second integrator coupled to the first integrator and a comparator coupled to the second integrator.

6. The analog-to-digital converter according to claim 5 , wherein the analog-to-digital converter comprises a filter coupled to the comparator that is one of a group consisting of a digital decimation filter, a low pass filter, a band-stop filter and a notch filter.

7. The analog-to-digital converter according to claim 1 ,
wherein the analog-to-digital converter is realized as a differential analog-to-digital converter and comprises
a second converter input and
a second reference voltage input,
wherein the capacitor array couples the second converter input and the second reference voltage input to the input side of the first integrator.

8. A sensor arrangement, comprising
the analog-to-digital converter according to claim 1 and
a sensor that is configured as a resistive sensor and is coupled to the first converter input,
wherein a first converter voltage that is tapped at the first converter input is a function of a parameter measured by the sensor.

9. The sensor arrangement according to claim 8 ,
wherein the sensor arrangement comprises
a first buffer coupled on its input side to the sensor and on its output side to the first converter input and being realized as a chopping buffer, and
a reference buffer coupled on its input side to a reference voltage terminal and on its output side to the first reference voltage input and being realized as a chopping buffer.

10. A method for analog-to-digital conversion,
wherein an analog-to-digital converter is implemented as a sigma-delta analog-to-digital converter and comprises a first integrator a first converter input a first reference voltage input, a capacitor array and a rotation frequency control unit,
wherein the method comprises
providing a first converter voltage that is tapped at the first converter input and a first reference voltage that is tapped at the first reference voltage input via the capacitor array that comprises capacitor elements to the first integrator, and
providing a rotation signal by the rotation frequency control unit with a rotation frequency having a first or alternatively at least a second value,
wherein a capacitor element changes its location at the rotation frequency, and
wherein a first subset of capacitor elements of the capacitor array is coupled to the first converter input and to an input side of the first integrator in a first phase and is coupled to the first reference voltage input and to the input side of the first integrator in a second phase as a function of the rotation signal.

11. The method according to claim 10 ,
wherein a comparator output signal is provided by a comparator that is coupled via a second integrator to the output side of the first integrator.

12. The method according to claim 11 ,
wherein a value of the rotation frequency at which one of the capacitor elements is changing its location is given by the equation:

fR
=

(

k
·

M
+
N

gcd
⁡

(

M
,
N

)

)

·
fN

,

wherein k is an integer number, M is the number of capacitor elements of the capacitor array coupled to the first converter input and to an input side of the first integrator in the first phase, N is the number of capacitor elements of the capacitor array coupled to the first reference voltage input and to an input side of the first integrator in the first phase, gcd is the greatest common divisor and fN is a value of a notch frequency of a filter coupled to the output side of the comparator.

13. An analog-to-digital converter, comprising
a first integrator,
a first converter input,
a first reference voltage input,
a capacitor array comprising capacitor elements, and
a rotation frequency control unit providing a rotation signal,

wherein a first subset of capacitor elements of the capacitor array is coupled to the first converter input and to an input side of the first integrator in a first phase and is coupled to the first reference voltage input and to the input side of the first integrator in a second phase as a function of the rotation signal.

14. The analog-to-digital converter according to claim 13 ,
wherein the rotation signal has at least two different values of a rotation frequency.

Assignees

• Ams Ag

Inventors

• García González Jose Manuel
• Gotarredona Rafael Serrano

Classifications

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M3/34 Primary

  by chopping · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/338 Primary

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title