Tin oxide thin film spacers in semiconductor device manufacturing

Patent metadata

Field	Value
Publication number	US-11031245-B2
Application number	US-201715713377-A
Country	US
Kind code	B2
Filing date	Sep 22, 2017
Priority date	Jun 28, 2016
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.

First claim

What is claimed is:

1. A method of processing a semiconductor substrate, the method comprising:
(a) providing a semiconductor substrate comprising an exposed SnO 2 layer and a layer of a silicon-containing material, wherein the layer of the silicon-containing material comprises an exposed portion, and a non-exposed portion, wherein the exposed SnO 2 layer is over and in direct contact with the non-exposed portion of the layer of the silicon-containing material, and wherein the silicon-containing material in the exposed portion of the layer of the silicon-containing material is the same as in the non-exposed portion of the layer of the silicon-containing material; and
(b) etching the exposed portion of the layer of the silicon-containing material in a presence of the exposed SnO 2 layer using an etch chemistry selected such that a ratio of an etch rate of the silicon-containing material to an etch rate of SnO 2 is greater than 1, wherein the etching exposes an underlying layer having a different composition from a composition of the exposed portion of the layer of the silicon-containing material.

2. The method of claim 1 , wherein the exposed SnO 2 layer comprises a plurality of SnO 2 spacers.

3. The method of claim 1 , wherein the exposed SnO 2 layer comprises a plurality of SnO 2 spacers residing over the non-exposed portion of the layer of the silicon-containing material.

4. The method of claim 1 , wherein the layer of the silicon-containing material comprises a silicon-containing compound selected from the group consisting of silicon nitride, silicon oxide and combinations thereof.

5. The method of claim 1 , wherein the layer of the silicon-containing material comprises silicon oxide.

6. The method of claim 1 , wherein the layer of the silicon-containing material comprises silicon nitride.

7. The method of claim 1 , wherein (b) comprises etching the silicon-containing material using a fluorocarbon plasma etch chemistry.

8. The method of claim 1 , wherein the exposed SnO 2 layer comprises a plurality of SnO 2 spacers, wherein distance between adjacent spacers is between about 5 and 90 nm.

9. The method of claim 1 , wherein the exposed SnO 2 layer comprises a plurality of SnO 2 spacers, having widths of between about 5 and 30 nm.

10. The method of claim 1 , wherein the etch chemistry in (b) is selected such that a ratio of an etch rate of the silicon-containing material to an etch rate of SnO 2 is greater than 1.5.

11. The method of claim 1 , wherein the etch chemistry in (b) is selected such that a ratio of an etch rate of the silicon-containing material to an etch rate of SnO 2 is greater than 2.

12. The method of claim 1 , wherein the layer of the silicon-containing material comprises silicon oxide, and wherein in (b) the silicon oxide is etched using fluorocarbon plasma such that a ratio of an etch rate of the silicon oxide to an etch rate of SnO 2 is greater than 1.5.

13. The method of claim 1 , wherein (b) comprises completely removing the exposed portion of the layer of the silicon-containing material without fully removing the exposed SnO 2 layer.

14. The method of claim 1 , further comprising etching and removing mandrels to form tin oxide spacers prior to (a).

15. The method of claim 1 , wherein the underlying layer exposed in (b) is a metal nitride layer.

16. The method of claim 1 , wherein the underlying layer exposed in (b) is a titanium nitride layer.

17. The method of claim 1 , further comprising removing the exposed SnO 2 layer after (b).

18. The method of claim 1 , further comprising after (b): etching the underlying layer that was exposed by etching in (b) and removing the exposed SnO 2 layer without fully removing the exposed portion of the layer of the silicon-containing material.

Assignees

• Lam Res Corp
• Lan Res Corporation

Inventors

• Smith David Charles
• Wise Richard
• Mahorowala Arpan
• Van Cleemput Patrick A
• Van Schravendijk Bart J

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/20

  of masks comprising organic materials · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/283

  by chemical means · CPC title